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ADC12D1600: Test pattern output error

Part Number: ADC12D1600

I'm probing the output terminations (100ohm res) of the data channel LVDS pairs, when the ADC is configured in test pattern mode.  

It doesn't seem to match what i'd expect from the datasheet, for instance, the Output of DQd(11-9) is cycling [011,100, 011, 100] when i would expect it to be [111,00,111,000].

I've double checked the routing for polarity errors.  All I can think of is maybe the ADC is for some reason in 2-s complement mode, and this affects the test pattern output (i don't think its supposed to according to datasheet).

Any ideas?  

Thanks, David