I would like to receive data from 6 channels continuously.
The ADC is controlled by the FPGA.
Connects four ADS7864s to one FPGA.
To do this, you need to minimize the number of control pins connected to the FPGA.
Can I save 3 pins A0, A1, A2 if using FIFO mode or CYCLE mode?
Is there any way to save more pin count?
Thanks in advance.
