DAC108S085: TMS320F280049

xiao kelvin

Part Number: DAC108S085
Other Parts Discussed in Thread: TMS320F280049

Hi，

I have a problem with the DAC108S085. The instruction manual said that the min value of tss is 3-10 ns, and the max value is (1/fSCLK - 3). I use TMS320F280049 to connect this DAC modular, but it's output parameter of tss cannot meet the requirement of the DAC chip.

So i have two question,

1. whether the tss value should in the range mention above

2. can i change tss value of TMS320F280049? I cannot find the method to configure.

wish for reply.

thanks

over 4 years ago

0 Akhilesh K over 4 years ago

TI__Mastermind 19086 points

Hi,

SYNC Set-up Time prior to SCLK falling edge (tss) should be in between 3 - 10ns. Max value depends on your SCLK frequency. For example if SCLK = 30MHz,

tss max should be 30ns. It should be within this range for data to to be latched properly.

What difficulty are you facing while configuring the DAC?

Regards,

0 xiao kelvin over 4 years ago in reply to Akhilesh K

Prodigy 130 points

Hi Akhilesh

The output of the tms320f280049 is show below.

SCLK = 1MHz

according to the manual of DAC108S085:
max tss = 997ns
max tsh = 997ns

But in fact the output of TMS320F280049 is
tss = 2000ns
tsh = 480ns
the tss value cannot meet the requirement of DAC

so if this is the point why I cannot configure the DAC chip?

I try to configure the output of the DSP, but I cannot find the way to configure this parameter of DSP

0 Akhilesh K over 4 years ago in reply to xiao kelvin

TI__Mastermind 19086 points

Hi,

I am not qualified to answer questions on TMS320 DSP. Can you please post the same in DSP forum, so that concerned technical folks can help you out?

Also as please note that, make SCLK idle state as high.

Since this issue is not related to DAC, I am closing this thread.

Please post the same in DSP forums.

Regards,

0 Manoj Santha Mohan over 4 years ago in reply to Akhilesh K

TI__Guru 55700 points

Kelvin / Akhilesh,

I'm assuming you are using F280049 SPI as master to talk to DAC108S085?

Is SYNC pin in DAC108S085 similar to Chip select in SPI? Based on the description in DAC datasheet it looks more like frame synchronization pin. Please confirm.

Regards,

Manoj

0 Akhilesh K over 4 years ago in reply to Manoj Santha Mohan

TI__Mastermind 19086 points

Hi Manoj,

You are correct. When this pin goes low, data is written into the DAC's input shift register on the falling edges of SCLK. After 16th falling edge of SCLK, a rising edge of SYNC causes the DAC to be updated. If SYNC is brought high before the 15th falling edge of SCLK, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC.

There is minimum high time for nSYNC input as well.

Regards,

0 Manoj Santha Mohan over 4 years ago in reply to Akhilesh K

TI__Guru 55700 points

AK / Kelvin,

Assuming SYNC pin has similar functionality of SPISTE pin, you can try setting up SPISTE pin as GPIO output pin. This way you can control when GPIO pin can pulled low (or) high whenever necessary.

Regards,

Manoj

0 xiao kelvin over 4 years ago in reply to Manoj Santha Mohan

Prodigy 130 points

Hi Manoj,

I succeed to configure the DAC modular by setting the DSP SYNC signal as 'SPI_PROT_POL0PHA0'.

Thanks

Best regards

kevin

0 Manoj Santha Mohan over 4 years ago in reply to xiao kelvin

TI__Guru 55700 points

Kevin,

Great!

Glad to know that things worked out for you.

Regards,

Manoj

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DAC108S085: TMS320F280049