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ADS54J60: JESD204B over fiber

Yuval Minster
Intellectual 800 points
Part Number: ADS54J60


HI,

I am now designing a board with fast ADC and I want to transmit the JESD204B data over fiber. I am working at subclass1. I read your white paper (attached) and at page 9 you describe how to transfer the SYSREF over fiber. You recommended to send the SYSREF from one board to the 2nd board and in the 2nd board to use a clock generator to regenerate the SYSREF and the device clock at phase 0.
I have few questions regarding this:
1. In this case, the SYSREF cannot be one-time event but periodic, right?
2. Why not to transmit the periodic device clock (instead of the SYSREF) from one board to another and use a clock generator to regenerate the SYSREF and the device clock?
3. Do you have an evaluation board +schemes that you can share that shows how to implement the JESD204B over fiber?

Thanks,
Yuval

  • 0
    TI__Guru* 91947 points

    Yuval,

    Answers to your questions below.

    Regards,

    Jim

     

    1. In this case, the SYSREF cannot be one-time event but periodic, right?

      The LMK transmitting SYSREF across the optical link would need to be periodic to keep the receiver LMK phase synchronized. I believe the receiver LMK will need to be setup for continuous SYSREF mode so that the SYSREF divider can be used as the PLL feedback signal. However, the individual SYSREF outputs can be disabled.

    2. Why not to transmit the periodic device clock (instead of the SYSREF) from one board to another and use a clock generator to regenerate the SYSREF and the device clock?

      You would lose the phase information of SYSREF. Remember that SYSREF is a system timing reference so the phase is important. If you send the high frequency device clock across, then you cannot regenerate the same phase on the other side. However… If the system doesn’t need deterministic latency (many systems do not) then you could send the high frequency device clock and have the receiving LMK generate a random phase SYSREF. As an example… Many systems require multiple ADC channels to be synchronized, which is easily accomplished using the subclass 1 deterministic latency of JESD204B. But if there is a calibration that is performed, such that all ADCs get a common calibration signal, then you can use the calibration signal to synchronize the ADCs, but may require delays/phase shifts in the FPGA logic.

    3. Do you have an evaluation board +schemes that you can share that shows how to implement the JESD204B over fiber?

      Nothing to share as this was done many years ago. The board was actually pretty straight forward. The JESD lines fed into the 12 channel optical transmitter and the optical receiver lines ran straight to the FPGA. I believe there was AC coupling capacitors within the optical TRX already.