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ADS131A04: Inquiry

Cedrick
Expert 8270 points
Part Number: ADS131A04

Hi,

Good day. I hope you are well. 

Our customer want to use the ADS131A04 however they have a question for it (copied below), can you please help us shed light on this?

"Lets assume 128KHz data rate, 24 bit (24 bit data) word length, 4 channels of data, status and CRC for 6 blocks of 24 it data.  I get 18.432 MHz but the data sheet limits Sclk to 12.5 MHZ (1/2 of Clock in max.)  What gives?"

I hope you could help us provide an information on this. Thank you. 


Regards,

Cedrick

  • 0
    TI__Guru 66346 points

    Hello Cedrick,

    Thank you for your post.

    SCLK is only limited to 12.5 MHz in Synchronous Master Mode, where the internal ICLK is the source of SCLK. For Asynchronous Interrupt Mode and Synchronous Slave Mode, SCLK can go up to 25 MHz for DVDD > 2.7 V.

    Regards,

  • 0 in reply to Ryan Andrews
    TI__Expert 8270 points

    Hi Ryan, 

    Thank you for your response. 

    So this implies that you can not use Synchronous Master Mode for word lengths of 24 or 32?  Because 24bits * 6 words *.128MHz = 18.432MHz.  Am I correct in this assumption?

    Thank you.

    Regards,

    Cedrick

  • 0 in reply to Cedrick
    TI__Guru 66346 points

    Hi Cedrick,

    Apologies for losing track of this post over the holidays.

    The word lengths of 24 and 32 bits are still valid options in Synchronous Master Mode. However, you will not be able to run the ADCs at the max data rate. As assuming 6 24-bit words, the maximum data rate is limited to about 86 kSPS.

    Regards,