ADS1271 Question

Hi Shaotong,

When you power up the ADS1271, you cannot have the master clock and SCLK tied to the same source. The reason being, the ADC needs some master clocks to program its internal settings before it receives SCLKs. As the data sheet mentions, upon power up, the SCLK is an output until the ADC is able to configure its internal settings. You do not want to drive an output pins with and input signal as it could cause damage to the device. After the ADC has been configured, the SCLK and master clock can be the same source. You could use a switch to hold the SCLK open until the ADC powers up and it receives some master clocks. After which, you could close the switch to allow the SCLK and master clock to come from the same source.

Regards,

Tony Calabria

Thank you very much for your help Tony. However, there is something else I want to make sure:  In the SPI Serial Interface section, SCLK (SPI Format) subsection, it suggets that the device shifs data out on the falling edge and the use shifts this data in on the rising edge. Does this means the chip works on spi mode 0 or spi mode1?

Shaotong,

SPI mode 0 and SPI mode 1 is defined differently by each manufacturer. You will need to look at the specific data sheet for your micro-controller to see what there definition of mode 0 and mode 1 is.

Regards,

Tony

Hi!

Thank you!

I did look at my microcontroller's datasheet and set microcontroller's serial clock's polarity to 0 and data is captured on mcu's clock's falling edge and propagated on the rising dege of the clock.

Software protocol is set up as below, the mcu's running at 8MHz while its serial clock is running at 2MHz.

for(i=0;i<3;i++)
{
 output_low(sync); //sending the sync pulse
 delay 1us ;
 output_high(sync);
 first_8_bit[i] = spi_read();//get 24-bit of data by reading 8-bit spi for 3 times
 second_8_bit[i] = spi_read();
 third_8_bit[i] = spi_read();
}

however upon running the chip i found tht DRDY is constantly held high, and never goes to low regardless of if there is serial clock input or not. Also, even if there is no SYNC signal going into ads1271, having master clock input will always result in DRDY being held high.

Is there any possible reason for this problem?

Shaotong

Hi Shaotong,

A couple things -

- If you are going to sync the part, you are going to have to wait tndr before DRDY goes active (See Figure 49). This time is 128 conversion periods typical. With a 2MHz master clock, this time period would be upwards of 16ms in high speed mode and greater than 32ms for high resolution and low power mode.

- You are going to need a continuous master clock as the master clock is used to control the conversions. When /CS is high, there needs to be a clock and when /CS is low, there needs to be a clock running.

- If you simply power up the ADC and enable the master clock, without sending a SYNC, does the /DRDY signal pulse?

Regards,

Tony Calabria

Thank you Tony!

I did wait for morethan 128 conversion periods after the pulse, and /DRDY begin to show waveform, however, the waveform of DRDY do not look correct at all: 

         output_low(PIN_A0);
         delay_us(100);
         output_high(PIN_A0);
         delay_ms(100);

This is the SYNC pulse i am putting in the SYNC pin, and output is in the attachement, the massive black block on the top is the /DRDY signal, while the thin impulse below is the SYNC signal.

Inside the black chunk: there is serveral 100us wide impulse for every 500us, distance between each block is 100ms. DOUT looks like /DRDY wth opposite polarity...

Shaotong

Hi Shaotong,

Try powering up the ADS1271, keep the SCLK line tied low, and just feed the master clock with your 2MHz signal. Then probe just the /DRDY to see if it behaves like Figure 63 indicates. Do not feed the SCLK with a signal during this time. This would be the first step to make sure the ADC is behaving correctly on power up. You just want to make sure that the /DRDY signal is responding so you can confirm that the converter is converting.

Regards,

Tony Calabria

Thank you, I did ths and found out that /DRDY output just like figure 63 for a random moment, then it will remain high for a random amount of time again....

Is this suggesting that there is something wrong with my power supply?

Shaotong

Shaotong,

Could you post a schematic so we can take a look at your configuration as well as your power supplies? 

Regards,

Tony

Hello! I manage to find out whats wrong with /DRDY when SCLK is low is because I have not foce /SYNC in high.... However, by timing /SYNC like this Im still not able to yield /DRDY pulses:

/SYNC low

delay for 2us(twice of clk period)

/SYNC high

8-bit spi read operation X3 times

if a put  a delay exact 512 times of conversion period I'll be able to yield glitched /DRDY though...

Shaotong

Shaotong,

Holding /SYNC low will put the part into power down mode and you will not see /DRDY pulses. Once the /SYNC line is held low for 2^19 clock cycles it will enter power down. In early testing, I would first tie /SYNC high as you make sure you get the converter working as you expect. I would then begin playing with the /SYNC pin to see if you can find out where your problem lies. Also note that when you experiment with the /SYNC pin, when it transitions from low to high to complete the SYNC, it will take 128 conversions before /DRDY will pulse indicating a new conversion result.

-Tony

Hi! I did manage to get data from DOUT pin, but again I had problem reading data into the microcontroller using the master clock as serial clock, after ADS1271 being powered up and received a few clockage from external clock, I connect serial clock to the master clock and end up getting all 0 on my microprosessor....

Therefore I decide to switch to frame sync mode, however, I'm not sure if I can use the same master clock as serial clock in frame sync mode as it was not specifically mentioned in the datasheet....