Sigma Delta ADCs - when is the data "ready" to be read?

Hi Richard,

thanks a lot for your question.

The order of the SINC filter tells you in general how much 'history' is used to create a conversion result. For a SINC3 filter the last three conversions are used in the digital filter to create a conversion result. We usually say the SINC3 filter has a 3-cycle latency.

I want to point you to the following application note that one of my colleagues wrote some time ago:
Digital Filter Types in Delta-Sigma ADCs

Let's look at Figure 5 in that application note which shows the step response of SINC filters with different orders.
In this example the input shows a step change at sample 16. The step change is happening exactly at the time where a new conversion cycle of the SINC3 filter begins. As you can see it takes three conversion cycles till the output of the SINC3 filter has settled to the final value.

If the step change were to happen somewhere in between sample 15 and 16 then the SINC3 filter would still not show a completely settled conversion result until conversion cycle 19. That means if the step change on the input is not synchronized to the start of a conversion cycle of the SINC3 filter, then it would take 3 + 1 cycles until you see the settled conversion result at the output of the SINC3 filter.

I want to point out that in your example the conversion cycle would be 1/200kHz. Means you will get a conversion result from the SINC3 filter every 5us. The worst case latency to detect a step change on the input would then be 3x 5us = 20us.
But as you can see from Figure 5 you will already notice a relatively big change in output signal after two conversions cycles. Means if you are using a delta-sigma ADC for e.g. overcurrent detection in a motor control application you will likely not have to wait until the SINC3 filter has fully settled to detect that something is wrong.

Let me know if this addresses your question.

Regards,