Good day I may have committed a bit of a blunder on my PCB for the ADS circuit. In an attempt o achieve max sync I routed the oscillator pins (24 and 25) in parallel with the processor oscillator pins . I just figured this affects the load capacitance and will certainly affect the crystal operation. SO please I have attached the schematic and PCB below as i yet to couple it i wanna know how I can calculate/estimate the capacitance on the lines and possibly reduce the attached external capacitors to mitigate the effects of the additional IC pins I also took a queue from the evaluation and made an option for external clock. You can notice its routed fro two layers I am already on 8.2pF which is far from the recommended 20pF. I am coupling now though just need pointers for problems ahead.
THanks