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Timing diagrams for continous sampling of ADS8320

Clay Shoup
Intellectual 410 points
Other Parts Discussed in Thread: ADS8320

Are there timing diagrams available for the ADS8320 where the device is in continous sampling mode?

  • 0
    TI__Guru**** 181521 points

    Hi Gary,

    The ADS8320 has to have a toggle of /CS in order to convert sample N, N+1, etc.  If you take Figure 3 from page 10 of the data sheet and just entend the left side you basically have what you are looking for.  The minimum /CS high time is one SCLK period.

    To get the full complement of data out of the part, you need 22 SCLKS while /CS is low.  You need at least one SCLK (at the full SCLK speed) period high on /CS between conversions.  So, depending on how you are running the clock (continuous or burst) and the speed of the clock (2.4MHz or something slightly slower) that diagram would change.  Let us know what your SCLK speed is and we'll try to get you something specific to this application.