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TVP5158 Question

Michael Hallak-Stamler
Prodigy 205 points

Other Parts Discussed in Thread: TVP5158

I am using the TVP5158 and want to know how the device achieves synchronization of four different clock domains to a single output super-frame for both the data and control signals: HSYNC, VSYNC.

Thanks

Michael Stamler

 

  • 0
    TI__Genius 16810 points

    Michael,

    Each of the 4 decoders has its own dedicated line-locked clock, but the output formatter uses a separate clock for clocking out the superframe with embedded syncs inserted.  Internal FIFOs handle the interface between the indiviudal decoders and the ouput formatter. 

  • 0 in reply to Larry Taylor
    Prodigy 205 points

    Great, thanks. 

    I am using a FPGA to receive six D1 channels using two cascaded TVP5158. I will probably use line-interleaved mode. Documentation says that a super-frame is created that looks like a progressive BT.656 frame. However, I don't understand how four D1 channels, which is equivalent to a HD frame, can fit into a BT.656 frame that handles D1 sizes only. 

    Also: I want to use 16-bit and not 8-bit mode to reduce the frequency of operation.