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ADS131M08: SPI Communication execution Time for 2Mbps speed

Part Number: ADS131M08
Hello there,
I am using AFE IC (ADS131M08, 24-bit sigma-delta ADC) 
Configuration requirement is 8000 samples/second, resulting in 125 usec ADC data reading ready interrupt.
In this 125 usec, we have to read ADC samples from AFE over SPI & also process this samples for measurement of 3 Phase Voltage & Current (7 Channels). 
Measurement part would take up to 50% of bandwidth. So to read data over SPI we are left with remaining 50% of Bandwidth. (i.e. almost 65 usec.)
 
My doubts are:-
1. Is it possible to receive ADC sample data of 7 Channels (24-bit*7Channels raw ADC Data) over SPI in 65usec
2. How the data transmission happens in ADS131M08 over SPI i.e. interrupt is generated for each byte transmission or complete packet(consisting of 7 channels raw data) is sent @ one go.
3. What would be the execution time of SPI to send/receive this data (in both case, either byte-bye or complete packet) 
4. Can anyone please share any reference document for this.
  • Hello,

    Thank you for your post.

    1. The minimum required SCLK can be calculated as n words x 24 bits/word x fDATA = 10 x 24 x 8000 = 1.92 MHz. If you only can use half the data rate period for data transfer, this doubles the minimum required SCLK to 3.84 MHz. This is easily achieved as the maximum SCLK frequency allowed is 15.625 MHz for 1.65 V <= DVDD <= 2 V and 25 MHz for 2.7 V <= DVDD <= 3.6 V. It is recommended to read all output words, including disabled channels and output CRC, in each frame to maintain a consistent /DRDY behavior.
    2. The output shift register in the ADS131M08 is loaded with the complete frame at one time (STATUS word, channel data, and output CRC).
    3. This is completely dependent on your host controller's capabilities.
    4. In addition to the data sheet, we have some example C code available on the device product folder. https://www.ti.com/product/ADS131M08#design-development##software-development

    Regards,