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ADC12DJ3200: ADC pattern when generated is working but input data seems to be corrupted.

Rajesh khanna
Intellectual 690 points
Part Number: ADC12DJ3200

Hi,

When the ADC is configured in JMODE 5 , With JTEST to 5 and 4 we are able to see pattern as per the datasheet.

When we actually configure to normal mode i.e input from source through balun to ADC channel A.

We are not able to find the sine wave data.

we received data shown below( is after transport layer conversion for input 156.25 MHz)

0dbcbcfb09f401f907f000f806effff806bc01f908f501fb0bfa02fd0dfb02fd

But when we run pattern, we seems to get below data

0000010102020303FFFFFEFEFDFDFCFC0000010102020303FFFFFEFEFDFDFCFC.

Can you please help in identifying the problem.

Regards,

Rajesh khanna

  • 0
    TI__Mastermind 20541 points

    Hi Rajesh,

    Sending the data in excel form and plotting would be helpful to visualize it.

    When you grab the data from the ADC and make samples from it. Can you please let me know how many bit per lane are you grabbing 32 bits/64bits ...... If it is 32BIT. Here is how you will need to do to arrange the samples I am explaining how the frame of data will look for you. 

    DA0 Lane  Sample0(8bits) Sample8    Sample16  Sample24

    DA1 Lane  Sample2(8bits) Sample10  Sample18  Sample26

    DA2 Lane  Sample4(8bits) Sample12  Sample20  Sample28

    DA3 Lane  Sample6(8bits) Sample14  Sample22  Sample30

    DB0 Lane  Sample1(8bits) Sample9    Sample17  Sample25

    DB1 Lane  Sample3(8bits) Sample11  Sample19  Sample27

    DB2 Lane  Sample5(8bits) Sample13  Sample21  Sample29

    DB3 Lane  Sample7(8bits) Sample15  Sample23  Sample31

    Hope this helps. 

    Regards,

    Neeraj

  • 0 in reply to Neeraj Gill
    Intellectual 690 points

    Hi neeraj,

    We have a working evm board with kcu105, we are able to decode the adc data and plot it successfully. If you see the pattern code for jtest 5. This is after rearranging the samples as per your suggestions.

    The custom board we made we are following similar firmware approach. I am able to extract adc pattern correctly from both boards without even single bit error when jesd link established properly.

    Usually if pattern works, the data reception from input channel also works.We find it odd that when we feed input signal to adc through signal generator, data seems to come not correctly.

    Can you please give some pointers to debug analog sections or configuration to validate the adc input section.

    Regards,

    Rajesh Khanna

  • 0 in reply to Rajesh khanna
    Intellectual 690 points

    Hi Neeraj,

    It seems enabling K28.5 instead of K28.7 is creating this problem.

    We have enabled K28.5 for better link establishment instead of K28.7.

    Regards,
    Rajesh khanna.