Data Rate in ADS1298

Hi Weng Kou Chan,

The ADS1298 has eight simultaneous sample and holds with eight independent delta-sigma converters.  The term samples per second refers to the data rate of the converter.  The DRDY output will toggle at the data rate so that your host controller knows when to start the data retrieval.

At 1000sps, the device is providing (up to) eight channels of 24-bit data plus one 24-bit status word every milli-second.  This is where the 216-bits comes from so relating the data rate of the converter to your data retrieval you are looking at 'bit rate' of 216Kbps max.  Lets assume that in your application you were only interested in the first four channels of data; the ADS1298 would still operate at 1000sps, but your bit rate would drop to 5*24 or 120Kbps.

The Serial Clock section on page 31 of the data sheet provides details on how to determine the minimum SCLK frequency necessary to retrieve the conversion results.

Hi again -

It sounds to me like you understand the difference.  Let us know if you have any further questions.

However, I double checked with the ADS1298 data sheet, and it seems to tell that the output sequence remains the same, so does it mean the output is constantly 216 bits anyway? the only matter is that the corresponding data for any power data channel is zero, so does it mean the data rate is still 216bkps (less the channel being used, more the zero bits)?? therefore I used the word effective in my last post.

The data sheet assumes all channels of the ADS1298 are being used. In the four channel example I used, the assumption is that CH4 through 7 are powered down. If the channel is powered off or there is no need/desire to retrieve data from those channels, you do not need to read them, so the 120Kbps would still hold.

Staying with the four channel example, lets say you have data on channels 0, 1, 2 and 5. In this case you would need to read the 'zeros' from CH3 and CH4 as well. That would be Status plus Ch0 through CH5 or 168 bits. Hopefully that clears things up for you.

Yes, I understand now, because I can control the period I read the data.

In the 4 channels case, if I still read in all the data including the zeros from those power down channel, of course the bit rate is 216bkps. However, I can choose to not read the last useless bits and stop the communication, at this point, I determine the data rate.

Now, I am curious on the data transfer. I read the data sheet and recognize that DRDY gives only a pulse when there is a new data, so but this pulse (low indicates new data) only present at the first bit (MSB) of the transition. The Rx and Tx buffer in the master holds only, 8 bits, a byte, so does it mean that I need to have a counter to know when I read in all useful bits and stop the communication please?

Once again thank you for your time and patience.

Depending on the SPI peripheral of your controller, you may have some options here.  Most 8-bit SPI controllers have some sort of flag that indicates the buffer is full.  You'll have to manage getting the data stored and concatenated properly so that you have meaningful results.  The time needed to shift and store data between bytes will have to be factored into the equation 6 I pointed you to in the ADS1298 data sheet.

In general, the easiest way to do this is to use the DRDY as an interrupt to the controller.  When new data is present, the DRDY signal goes low and stays low until the SCLK is applied.  As you noted above, the DRDY goes inactive with the MSB of the status word.  In your interrupt service routine, you would first set the /CS input to the ADS1298 low, load your command into the TX buffer to generate the SCLK, and simply loop through 3x for the Status word and each active data channel.  This is essentially what is happening in the source code discussed in your previous posting.

Hi Tom

So which means the DRDY only gives me a signal whenever there is a new data coming, but it doesn't give me a signal when the transfer is done. (which sounds also impossible since the data pattern is always 216 bits, but the number of useful bit is determined by me, so there is no way the DRDY knows when I need to stop).

With leads me to a implement a loop to count the incoming byte, so let say in the case of 4 channels again, since status bits and channel result are both in 24 bits ( 3 bytes), and the total transaction is expected to transfer 120 bits (15 bytes), so I need to set up a loop with a counter of 15 in order to receive all the bytes. 

Does it sound correct to you?

Weng,

Please remember the communication to this device is via a synchronous serial or 'SPI' type interface, TX and RX take place at the same time (full duplex).  MOSI from the master goes to SDI of the ADS1298, SOMI would be connected to SDO.  The master controller must transmit 3 bytes times the Status plus the number of active channels.  So yes - you need to incorporate a counter (Status plus 4CH would be 15bytes total) so that the master controller can generate the necessary SCLKs which in turn causes the ADS1298 to provide the conversion results back to the recieve buffer.  Your SPI clock must be fast enough so that any delay caused by the byte wide transfers in your micro controller are accounted for and all data is recieved before the BUSY signal goes active again.

Tom, thank you very much, I will read the MSP430 user guide to find out this BUSY signal.

However, I think I get another understand of the data rate. The sample referred in SPS is in fact all those 216 bits, and when these samples are needed to transfer to the outside world, it is done by the SPI interface. The SPI interface has its clock to shift IN/OUT the data, thus the output data rate is in fact determined by this clock speed. Therefore let say I need only the first 4 channels data, my MCU will ask for the data from ADS, then collect the first 120bits, then stop transmission, ask again, and so on. The data rate at this point is thus 120bits * fsclk.

Am I understanding it correctly?

Hi Weng,

The datarate of the ADS1298 does not factor in the SCLK speed of your SPI interface.  The datarate only factors in the DR settings in the ADS1298 registers and the frequency of the oscillator driving the main clock.  The transfer rate from the ADS1298 to your host processor will depend on you SPI clock and that must be high enough to get all the requested data out of the device before DRDY goes active for the subsequent data sets.