Part Number: ADS1282
I have a ADS1282 based design - i am reading data using RDATAC command. DRDY triggers as expected, but DOUT is at 0. The SPI interface itself reading and writing registers is working as expected. By when a SPI read is triggered on DRDY, DOUT does not change at all. Input clock is steady at 4.096MHz, and SCLK is being generated after DRDY trigger. BYPAS is around 1.8V. Would appreciate any pointers on how to debug this.
Thanks
Hi Santosh,
I'm not sure what the issue may be here since you say that register reads and writes are working for you. Assuming that SPI communication is working, the most likely cause for reading all zeros or all ones on DOUT would be the timing of when the SCLK pulses are sent with regard to /DRDY...
If you are attempting to clock out data before /DRDY goes low, then this would likely result in a fixed valued on DOUT (0x000000 or 0xFFFFFFFF). The only other instance I'm aware of where the device would behave like this would be in continuous sync mode during a re-synchronization (while re-synchronizing /DRDY will toggle but DOUT will be held low for the 63 conversion periods required for the FIR filter to settle). By chance are you programming the CONFIG0 register to put the device in continuous sync mode?
To troubleshoot this issue, I would double check on a scope that you are only sending SCLKs after the /DRDY signal goes low. There should be 32 SCLK pulses and /DRDY should return high after the first SCLK pulse.
Additionally, you might try programming the CONFIG0 register to use the "Sinc filter block only" (to shorten the digital filter settling time) and waiting longer before reading data or reading data multiple times to see if DOUT does change eventually.
If you have additional information you could share, it would be helpful to see a schematic and to know how you are programming the device registers.
