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Original question:

ADS52J90: Maximum JESD speed?

ADS52J90: ADC_RES register

Eric Raguzin
Prodigy 130 points
Part Number: ADS52J90


I have a quick question about the ADC_RES register. In Tables 14, 15, and 18, it looks like ADC_RES can be set to 16. However, in every other reference - Table 54, text in Section 8.3.3 and 8.4.2, it looks like it can only go up to 14. The ADC is advertised as being up to 14 bits, so I'm just wondering, can ADC_RES actually be set to 16? In Figure 72, it looks like there are either 2 ADC_RES registers, or the same register affects 2 blocks, so I'm wondering if I'm mixing anything up.

It makes sense that SER_DATA_RATE can go to 16 bits, as that only fills out any extra bits in a word with padded zeros. As a side question, when communicating through the JESD interface, does setting SER_DATA_RATE to 16 give the same exact output as setting SING_CONV_PER_OCT to 1? Do the padded zeros show up in the same exact bits?

  • 0
    TI__Intellectual 1590 points

    Hi Eric,

    Sorry for the confusion. In ADS52J90, the analog conversion block doesn't support 16 bit ADC resolution. It only supports 10,12 and 14 bit resolutions. Also there is in only one register setting to set the ADC_RES (Register 4h, Bits <1:0>) and ADC_RES is routed to multiple blocks inside the device digital.

    Regarding zero padding in the JESD output, your understanding is correct. Only When SER_DATA_RATE = 16, the zero padding will be done in similar fashion in both SING_CONV_PER_OCT mode and Normal data packing. But for other SER_DATA_RATE values, the it will be done in different way in both these modes. Please refer to Table 19 to 24 in the datasheet for more details.

    Kindly let us know if you have any further queries.

    Regards,

    Kalyan