Other Parts Discussed in Thread: LMK04828
Hi Team,
Can you please check and advise with following request:
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I would like to ask a few questions about TI's ADS54J60 chip, if possible. We have a problem with obtaining SFDR values which are denoted in ADS54J60 datasheet.
- We use 250 MHz ADC reference clock, which is the output of LMK04828 chip.
- SYSREF pulses are generated using LMK04828 either. We calculated the SYSREF frequency from SYSREF = LMFC / 2^N. By selecting N=4, (fs/4)/K => (1000/4)/16 = 3.90625 MHz.
- We use 4244 LMFS configuration and corresponding DDC mode & JESD link properties given in datasheet. You can find our register configurations attached (adc_config.txt).
- Fs/4 noises seem acceptable (approximately ~90dBFS).
However, our SFDR is not as fine as datasheet offers. Even if a 0 dBFS signal is applied, our maximum SFDR is around 53 dB. We always observe a harmonic spur (I think it is a second harmonic, aliased somehow) which has 2x bandwidth of original signal.
I also attached the spectrums of ADC output signal. Do you have a suggestion to improve our SFDR performance? I can provide additional information about out setup if it is required.
We have a secondary problem, last two LSB output bits of "channel A" are stuck. Depending on the input signal frequency, it is always stuck at some value ("00","01"..). Am I missing something in register configuration?
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Thanks in advance
Best Regards
Furkan Sefiloglu