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ADS1271: Questions about ADS1271 latency.

Kazuya Nakai59
Guru 22355 points

Part Number: ADS1271
Other Parts Discussed in Thread: ADS127L01

 Hello guys,

 One of my customers is evaluating ADS1271 for their next products.

 I have a few questions about ADS1271 latency. Could you please tell me your reply?

 Q1. The customer found the converted digital data of ADS1271 was delayed about 5ms from the corresponded analog input .

       I know that the delay is caused by the device latency.

       Also they use the device in high speed mode (MODE pin=L) and CLK=2.5MHz. But I want to know the following things.

       How to calculate the latency in case of this device?

       Can "Group delay" parameter be used for it? 

       If it is yes, is the latency 38/(2.5M/256) = 3.9ms approx(Typ)?

 Q2. Is the latency changed by the analog input signal amplitude and ffrequency?

 Q3. What is the way to set the minimum latency for ADS1271.

       Is it only to set the device to high speed mode (MODE pin=L)? 

 Your reply would be much appreciated.

 Best regards,

 Kazuya.

  • 0
    TI__Guru 51290 points

    Hello Kazuya,

    Q1.

    The latency (or settling time) is expressed in number of data rate periods.  For the high speed mode, this is equal to 76*Tdata.

    latency = 76*(256/2.5M) = 7.7824mS.

    Group delay specifies the time to about 50% of final value on a step input.  You can estimate to other values by referring to Figure 62 in the datasheet.  At 5mS, the output has settled to about 99% of final value.

    Q2.

    No, this is fixed by the digital filter architecture, and does not vary with input signal amplitude or input frequency.  It does depend on the main CLK frequency/period.

    Q3.

    To minimize latency, you need to maximize output data rate.  Select high-speed mode and run at the maximum CLK frequency of 27MHz.

    If the customer needs lower latency, please suggest the ADS127L01, which has faster settling filter options.

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • 0 in reply to Keith Nicholas
    Guru 22355 points

     Hello Keith,

     Thank you very much for your reply.

     Could I ask you an additional question as the follow?

     Q. The customer wants to use 2.5MHz clock for CLK (master clock).

          How much is the minimum latency with 2.5MHz CLK in case of ADS127L01?

          What percentage is reduced compare with ADS1271 latency?

     Could you give me your reply?

     Thank you again and best regards,

     Kazuya.   

  • 0 in reply to Kazuya Nakai59
    TI__Guru 51290 points

    Hello Kazuya,

    Using the low latency filter option on the ADS127L01 and OSR=32 setting, the minimum latency will be:

    Latency (settling time) = 5*32*(1/Fclk) = 160*1/2.5M = 64uS.

    The Latency for the ADS1271 will be much higher, since it does not have a low latency filter option:

    Latency (settling time) = 76*(256/2.5M) = 7.7824mS.

    (1-64uS/7782.4uS)*100 = 99.2% reduction in latency compared to ADS1271.

    Regards,
    Keith

  • 0 in reply to Keith Nicholas
    Guru 22355 points

     Hello Keith,

     Thank you very much for your reply.

     It is very helpful for the customer and me.

     Thank you again and best regards,

     Kazuya.