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AMC1336: Can there be distortions on the transfer function, like overshoot, where getting high the input values the output values decrease, in a fault scenario?

Part Number: AMC1336


Good morning,

I contact you as external RAMS consultant engineer for Hitachi Rail STS for an explanation on an eventual fault scenario that concerns the AMC 1336 component.

The question concerns the possibility of the Delta Sigma component in object if it can change its transfer function, introducing a partial distortion, such that input values in a certain interval are read as higher values, like an overshoot.
For a better fault scenario comprehension I also attach a picture that can describe what I mean.

I hope we can start a discussion on this subject, leading to some rate estimations for this kind of distortions to happen.

Thank you to pay attention,
I look forward to seeing your feedback.

Kind regards.
Antonio Gallo

  • Hi Antonio,

    Welcome to our e2e forum and thank you for your interest in the AMC1336! 

    Have you actually seen this behaviour or is this just a 'what if' discussion?  Can you possibly put a time scale to the drawing you provided?  Let me first point to a few things you can find in the AMC1336 datasheet that might provide you with some possible fault scenarios. 

    1. Take a look at Figure 2 on page 9, when you first power up the high (AVDD) side of the AMC1336, there is a period of 250uS where the output bit stream is considered invalid.  During this 'analog start' time, the internal reference is settling and the modulator is waking up.  If you are capturing that data in your digital filter process, it could look like a distortion.
    2. Take a look at figures 40 and 41 - depending on how the inputs are applied to the AMC1336, you could see a transient common mode shift that could look like an over (or under) shoot.
    3. Finally, look at Figure 48.  If there is a transient input that exceeds the Vclipping level, you will see a solid 'one' or 'zero' on the output bit stream that lasts through 127 clock cycles.

    The only other scenario that I can think of is of there is a loss of AVDD power, in which case you can refer to Figure 49.  The output bit stream will be all zeros, followed by point 1 above.

  • Hi Tom,

    The points highlighted in the answer are very interesting, but my question was asked to clarify any possible failure mode of the component.

    I have not seen this behaviour yet, this is a "what if" discussion and in the following I will try to describe the situation.

    During the normal working, for growing input values (in a determined range compliant with the datasheet), having the monotone and growing delta sigma transfer function, in output I will expect to have growing values.

    In a fault scenario, where the fault occurs inside the component, can there be distortions on the transfer function, like an overshoot, where getting high the input values the output values decrease?

    In case this failure mode could happen I would appreciate very much to have a more detailed explanation regarding the rate of failure.

    Thanks a lot and kind regards.

    Antonio Gallo

  • Hi Antonio,

    OK - thanks for the clarification.  The AMC1336 is relatively simple, so lets take a walk through the block diagram in Figure 7.2 on page 17.  If the analog inputs were to fail (short together, to ground or to AVDD), you would have a constant output, but no distortion like you show above.  The modulator is basically a 1-bit ADC, so it only ever gives a one or zero to be passed over the isolation barrier.  The determination of the one or zero is based on the reference, so if either of those blocks failed, the output would saturate.  The iso caps are associated with a transmitter/reciever block - if the cap, the transmitter or reciever failed, the output would saturate to all ones or all zeros depending on the state of the last bit transmitted over the barrier.  Again, no overshoot or distortion, just a constant output.  The digital interface block is basically a schmidt trigger buffer on DOUT and CLKIN.  If that were to fail, again you'd see a stuck output at zero or one but no interval of higher values. 

    Hopefully that helps to answer your question!  If not, let me know and we can discuss it further.

  • Hi Tom.

    Ok perfect. Your answer was very valued, but I would like go even deeper into the matter (if possible).

    Staying on the figure 42, I would like to ask you other few questions:

    1.  The figure represents the corresponding block scheme of the component or it is only a generic delta sigma block scheme?

    2. Does AMC1336 have credible failure modes of any functional blocks shown (like integrators, adders and comparator) which may cause a significant  distortion of the trans-characteristic, such that the output returns a much greater value than the input, for an input values interval?

    Thank you and kind regards.

    Antonio Gallo

  • Hi Antonio,

    For Q1, if you look back at the Functional Block Diagram from section 7.2, Figure 42 is just the delta-sigma modulator portion.  Vin is derived from the differential INp and INn and the output of the comparator (CMP) is in the DAC feedback loop and also goes to the isolation cap drivers.  For Q2, to the best of my knowledge there is nothing internal to the device that, in a failure condition, would lead to a large scale change in the transfer function through a particular region or interval of the input voltage.  Failure of a block would cause a constant offset, or perhaps a constant gain error or simply a 'stuck' output of all ones or all zeros.

  • Hi Tom,

    You have explained clearly the point regarding the fault scenario on the block scheme. 

    In the last answer you have said "to the best of my knowledge" and because this component would be used in the railway enviroment could be important to know if your analysis is based only on a component knowledge or is based on any standard (e.g. CENELEC 50129).

    Thanks a lot and kind regards,

    Antonio Gallo

  • Hi Anthony,

    I've not looked into the CENELEC 50129 document, my comments/analysis are based on knowledge of the device only.

  • Hi Tom,

    Ok no problem, but I would like to have any estimation on the failure rate or credibility rate for the initially fault scenario described. 

    I ask you this estimation because only you (or another TI engineer) knows how is the real internal structure of the component and an estimation on the block scheme (figure 42 of the datasheet) can not be enough for the safety of the my application.

    Thanks a lot and kind regards,

    Antonio Gallo

  • Hi Antonio,

    If it's OK with you, I'll send you a note via your registered my.TI e-mail account.

  • Hi Tom,

    Yes, it is ok. You can use:

    antonio.gallo 'at' alten.it

    or

    Antonio.Gallo.ext 'at' hitachirail.com

    Thank you and kind regards,

    Antonio Gallo