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Original question:

ADS127L01EVM: VOCM Source for THS4551

ADS127L01: CLK requirements

Robert Cermak
Prodigy 60 points

Part Number: ADS127L01

Hello,

I would like to better understand the clocking requirements of this ADC.

1) Is there any problem to feed SCLK and CLK from the same source - i.e. to feed single CLK signal to both pins by common trace ? The clock frequency would be 16.384Mhz.

2) Is there any recommendation regarding CLK rise/fall times ? - I.e. what is the max. reasonable Tr/f ?

3) What is the required CLK duty cycle tolerance to meet all ADC specs ?

The ADS127L01 data sheet (pg. 7) states “To meet maximum speed conditions, fCLK duty cycle must be 49% < duty cycle < 51%”.

On the other hand the evaluation board ADS127L01EVM uses Abracon oscillator ASEMB-16.000MHZ-XY-T which datasheet states “symmetry 45% - 55%”.

Thank you for clarification.

  • 0
    TI__Guru 51370 points

    Hello Robert,

    1) Is there any problem to feed SCLK and CLK from the same source - i.e. to feed single CLK signal to both pins by common trace ? The clock frequency would be 16.384Mhz.

    You can only run SCLK continuous if you are using frame sync interface mode.  If using SPI mode, there is a keep-out time requirement during the conversion cycle that requires SCLK remain low for at least 4 CLK periods.  Please refer to Figure 91 in the datasheet for more details.

    2) Is there any recommendation regarding CLK rise/fall times ? - I.e. what is the max. reasonable Tr/f ?

    Unfortunately, there is no specification.  However, we do recommend adding a series resistor on the input to limit ringing, which increases the rise and fall times.  A typical value would be around 5V/nS.

    3) What is the required CLK duty cycle tolerance to meet all ADC specs ?

    The limitation of 49% < duty cycle < 51% only applies at the maximum clock frequency of 16.384Mhz and is due to the minimum CLK high or low pulse duration of 28nS.  For clocks 16MHz (used on EVM) and lower, the minimum pulse width of 28nS relaxes the duty cycle to 45%< duty cycle <55%.

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • 0 in reply to Keith Nicholas
    Prodigy 60 points

    Hi Keith, thanks you for the answer.

    As for:

    1) I am still in impression that continuous SCLK mode is feasible when we take CS signal high after last bit of data is clocked out from ADC.

    The datasheet 8.5.1.1 states “When CS is taken high, the serial interface is reset, SCLK is ignored ...” therefore the keep-out time is satisfied - isn’t it so ?

    If it is so, may we expect any performance issues when we tight both SCLK and CLK pins together and feed them by common signal trace ? I assume clock inputs have up to 1.6pF each - right ?

    2) Do you recommend 5V/ns at oscillator output or at ADC input ? Isn’t the Tr <1ns too fast ? I see the 16MHz oscillator at EVM has max raise time up to 3ns plus there is RC filter at ADC side.

    3) 49% < duty cycle < 51% seems to me pretty tight for the common clock oscillators. Would you suggest an example - a concrete 16.384MHz XO - complying to this and all other requirements of this ADC ?

    Thanks for your clarification !

  • 0 in reply to Robert Cermak
    TI__Guru 51370 points

    Hi Robert,

    I see your point on question 1.  Yes, I agree that if you pull /CS high and allow for at least 4 CLK periods before /DRDY goes low, then you will meet the keepout requirement.  One other timing limitation when using /CS pin is the minimum high time of 6 CLK periods.  Thus, in order to meet the minimum /CS high time of 6 t-CLK, and keepout time of 4 t-CLK, you will not be able to meet all timing requirements when using the OSR=32 setting.  24 CLK's for the data, plus 4 CLK's for the keepout, and and another 6 CLK's for the minimum high time is 34 CLK's, which will exceed the output data rate of 32 CLK's.  However, this should work for the other OSR settings with SCLK=CLK.

    Yes, the input pin capacitance for SCLK and CLK will be around 1.6pF, plus any board level capacitance.

    Regarding the rise time, the CLK buffer has a much faster rise time than the oscillator on the EVM.  Using the RC filter slows the rise/fall time down to 2V/nS, which has shown better noise performance on the EVM, but this can be faster if needed and will depend on your system requirements and the specific board layout.  Since these cannot easily be specified, we simply recommend adding an RC to the CLK pin so that you can fine tune the system with your specific clock oscillator and board layout.

    If you can run at the slightly slower 16MHz frequency, then this relaxes the duty cycle requirements.  You can also specify an oscillator at 2x the frequency, and then divide by 2.  As long as the minimum clock high/low duration of 28nS is met, then you will be fine.

    Regards,
    Keith

  • 0 in reply to Keith Nicholas
    Prodigy 60 points

    Thank you for comprehensive information !

    Regards

    Robert

  • 0 in reply to Robert Cermak
    TI__Guru 51370 points

    You are welcome!