ADS4126: Can the ADS4126 clock be provided from an FPGA PLL?

Thanks, this has been quite helpful. Is there a way to prove that the clock from our FPGA PLL is going to have the required characteristics?

Also, lets assume that we have a poor clock source but don't know that it is poor. Is there a way to prove in through hardware testing that an ADC performance has been compromised due to a poor clock?

OK, this should be the last question - for the time being atleast.

Lets say I want to go shopping for a clock source for this ultra low power ADC. How do I know that the clock source I am choosing is suitable for use with this ADC? i.e the properties of its output clock make it suitable for use with this application? Is there some specific feature to look for?

Sorry, I think my question was not clear. When shopping for oscillator, how do I know it has sufficiently low jitter? Is this question for posting on the high speed clock forum? I have seen the device in the schematic. However, I just want to understand the theory so I do not get confused about this again.

Thanks.

wow this is great. 

So what I understand from this is that the clock source must be sinusoid for best performance as it does not contain clock harmonics. Is there a specific class of clock generators that generate sine wave output instead of square wave output?

It says that we need to filter the clock which is tricky with square wave clock since its harmonics create the high slew rate in the first place and filtering shall reduce its slew rate. By filtering it means filtering to reduce jitter i.e phase noise. Is that correct?

OK, the point of PLL is clear now.

This device has two output types which are DDR LVDS and SDR CMOS. Assuming that I am using CMOS, from the ADC starting to receive data, do we have to wait 10 clock cycles before we start to latch data coming from the ADC? I am asking this because the ADS4126 datasheet "Theory of Operation" section on page 58 states:

"The sampled signal is sequentially converted by a series of small resolution stages, with the outputs combined in a digital correction logic block. At every clock edge the sample propagates through the pipeline, resulting in a data latency of 10 clock cycles."

Also, when data is coming in, do we have a complete ADC conversion into 12 bits coming in ever clock cycle? In other words, is that the output bits D0 to D11 all correspond to the same data word or D0 corresponds to 12 clock cycles old ADC sample and D1 the one from 11 clock cycles ago e.t.c until D11 being from the current ADC conversion? The reason for this question is the confusing timing diagram in Figure 8 of the ADS4126 datasheet shows the Parallel CMOS Output data as N-10, N-9 e.t.c until being N.

I do not have any more questions. How do I close this "ticket"?