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Original question:

ADC32RF45: Unable to read Digital bank registers but able read Analog bank and direct addressees bank registers

ADC32RF45: ADC32RF45 JESD configuration

Bala Krishna E88
Prodigy 110 points
Part Number: ADC32RF45

Hi,

I am using ADC32rf45 Custom Board. 

I configured the ADC chip with registers that are suggested by TI team,

i configured the JESD in Zynq board and could not see SYNC from ADC. so the SYNC is not asserted.

How can we check the JESD path working or not from ADC.

I have tried SYNC polarity reversed in registers.

Can you suggest How do we test JESD path from ADC to FPGA.

Regards

Balakrishna

  • 0
    TI__Genius 10705 points

    Hi Balakrishna,

    For debug, ADC JESD output can be overridden with K28.5 characters through SPI. See below registers. 

    To confirm that ADC is configured correctly, we can verify the configuration file on TI EVM. Did you already do this? If not, please send me the mode details and configuration file you are using. I can verify on TI EVM. 

    Regards,

    Vijay

  • 0 in reply to Vijayendra Varma Siddamsetty
    Prodigy 110 points

    hi

    i am sending the ADC configuration file, 

    we have configured ADC with 2.5Gsps sampling and sysref with 2.44MHz.

    FPGA side: 8224 mode with lane rate 12.5Gbps and refclk with 312.5MHz and using Qpll0 .

    when we configure 8 lanes with 12.5Gbps, how much will be data rate that is configured on each lane(on one lane).

    we have used bank 224 and 225 for MGT lanes and using 224Qpllo as ref clock.

    single JESD block is used to configure the 8 lanes without JESD_PHY. 

    Synq signal from JESD IP is not asserting and  JESD ip coming out of the Reset. 

    We tried the suggested previous mail configuration, but no change.

    Regards

    Balakrishna

    adc_bypassmode_8224_by_ti_24bit.txt 
    ADC32RFxx_LOWLEVEL
0x000081,   // Global software reset. Remember the sequence of programming the config files is Powerup_Analog_Config-->IL_Config_Nyqx_chA-->IL_Config_Nyqx_chB-->NL_Config_Nyqx_chA-->NL_Config_Nyqx_chB-->JESD_Config
0x0011FF,   // Select ADC page.
0x0022C0,   // Analog trims start here.
0x003280,   // ...
0x003308,   // ...
0x004203,   // ...
0x004303,   // ...
0x004558,   // ...
0x0046C4,   // ...
0x004701,   // ...
0x005301,   // ...
0x005408,   // ...
0x006405,   // ...
0x007284,   // ...
0x008C80,   // ...
0x009780,   // ...
0x00F038,   // ...
0x00F1BF,   // Analog trims ended here.
0x001100,   // Disable ADC Page
0x001204,   // Select Master Page
0x002501,   // Global Analog Trims start here.		
0x002640,   //...
0x002780,   //...
0x002940,   //...
0x002A80,   //...
0x002C40,   //...
0x002D80,   //...
0x002F40,   //...
0x003401,   //...
0x003F01,   //...
0x003950,   //...
0x003B28,   //...
0x004080,   //...	
0x004240,   //...
0x004380,   //...
0x004540,   //...
0x004680,   //...
0x004840,   //...
0x004980,   //...
0x004B40,   //...
0x005360,   //...
0x005902,   //...
0x005B08,   //...
0x005c07,   //...
0x005710,   // Register control for SYSREF --these lines are added in revision SBAA226C.
0x005718,   // Pulse SYSREF, pull high --these lines are added in revision SBAA226C.
0x005710,   // Pulse SYSREF, pull back low --these lines are added in revision SBAA226C.
0x005718,   // Pulse SYSREF, pull high --these lines are added in revision SBAA226C.
0x005710,   // Pulse SYSREF, pull back low --these lines are added in revision SBAA226C.
0x005700,   // Give SYSREF control back to device pin --these lines are added in revision SBAA226C.
0x001200,   // Master page disabled
0x0011FF,   // Select ADC Page
0x008307,   // Additioanal Analog trims
0x005C00,   //...
0x005C01,   //...
0x001100,   //Disable ADC Page. Power up Analog writes end here. Program appropriate -->IL_Config_Nyqx_chA-->IL_Config_Nyqx_chB-->NL_Config_Nyqx_chA-->NL_Config_Nyqx_chB-->JESD_Config
0x400100,   //DC corrector Bandwidth settings
0x400200,   //...
0x400300,   //...
0x400461,   //...
0x606842,   //...
0x400301,   //...
0x606842,   //...
ADC32RFxx_LOWLEVEL
0x400100,   //Select Main Digial Page. Remember the sequence of programming the config files is Powerup_Analog_Config-->IL_Config_Nyqx_chA-->IL_Config_Nyqx_chB-->NL_Config_Nyqx_chA-->NL_Config_Nyqx_chB-->JESD_Config
0x400200,  
0x400300,   //Main digital page selected for chA
0x400468,  
0x604401,   //Program global settings for Interleaving Corrector
0x606804,   //...
0x60FFC0,   //...
0x60A208,  	//Progam nyquist zone 1 for chA, nyquist zone = 1 : 0x08, nyquist zone = 2 : 0x09, nyquist zone = 3 : 0x0A 
0x60A903,   //...
0x60AB77,   //...
0x60AC01,  	//...
0x60AD77,  	//...
0x60AE01,  	//...
0x60960F,  	//...
0x609726,  	//...
0x608F0C,   //...
0x608C08,   //...
0x60800F,  	//...
0x6081CB,  	//...
0x607D03,   //...
0x605675,   //...
0x605775,   //...
0x605300,   //...
0x604B03,   //...
0x604980,   //...
0x604326,   //...
0x605E01,   //...
0x604238,   //...
0x605A04,   //...
0x607120,   //...
0x606200,   //...
0x609800,   //...
0x609908,   //...
0x609C08,   //...
0x609D20,   //...
0x60BE03,   //...
0x606900,   //...
0x604510,   //...
0x608D64,   //...
0x608B20,   //... 
0x600000,  	// Dig Core reset
0x600001,  	//...
0x600000,  	//...
ADC32RFxx_LOWLEVEL
0x400100,   //Select Main Digial Page. Remember the sequence of programming the config files is Powerup_Analog_Config-->IL_Config_Nyqx_chA-->IL_Config_Nyqx_chB-->NL_Config_Nyqx_chA-->NL_Config_Nyqx_chB-->JESD_Config
0x400200,  
0x400301,   //Main digital page selected for chB
0x400468,  
0x604980,   //Special setting for chB
0x604220,   //Special setting for chB
0x60A208,  	//Progam nyquist zone 1 for chB, nyquist zone = 1 : 0x08, nyquist zone = 2 : 0x09, nyquist zone = 3 : 0x0A 
0x400300,   //Main digital page selected for chA
0x600000,  	//...
0x600001,  	//...
0x600000,  	//...
0x600000,  	//delay 50ms for IL correction  
0x600000,  	//delay
0x600000,  	//delay
0x600000,  	//delay
0x600000,  	//delay
0x600000,  	//delay
0x600000,  	//delay
0x600000,  	//delay
0x600000,  	//delay
0x600000,  	//delay
0x600000,  	//delay
0x600000,  	//delay
0x600000,  	//delay
0x600000,  	//delay
0x600000,  	//delay
0x600000,  	//delay
ADC32RFxx_LOWLEVEL
0x400300,   //chA Non Linearity Trims for Nyq1. Remember the sequence of programming the config files is Powerup_Analog_Config-->IL_Config_Nyqx_chA-->IL_Config_Nyqx_chB-->NL_Config_Nyqx_chA-->NL_Config_Nyqx_chB-->JESD_Config
0x400420,   //...
0x4002F8,   //...
0x603CF5,   //...
0x603D01,   //...
0x603EF0,   //...
0x603F0C,   //...
0x60400A,   //...
0x6041FE,   //...
0x6053F5,   //...
0x605401,   //...
0x6055EE,   //...
0x60560E,   //...
0x60570B,   //...
0x6058FE,   //...
0x606AF4,   //...
0x606B01,   //...
0x606CF0,   //...
0x606D0B,   //...
0x606E09,   //...
0x606FFE,   //...
0x6081F5,   //...
0x608201,   //...
0x6083EE,   //...
0x60840D,   //...
0x60850A,   //...
0x6086FE,   //...
0x6098FD,   //...
0x609900,   //...
0x609A00,   //...
0x609B00,   //...
0x609C00,   //...
0x609D00,   //...
0x60AFFF,   //...
0x60B000,   //...
0x60B101,   //...
0x60B2FF,   //...
0x60B3FF,   //...
0x60B400,   //...
0x60C6FE,   //...
0x60C700,   //...
0x60C800,   //...
0x60C902,   //...
0x60CA00,   //...
0x60CB00,   //...
0x60DDFF,   //...
0x60DE00,   //...
0x60DF02,   //...
0x60E000,   //...
0x60E1FE,   //...
0x60E200,   //...
0x60F400,   //...
0x60F500,   //...
0x60FB01,   //...
0x60FC01,   //...
ADC32RFxx_LOWLEVEL
0x400300,   //chB Non Linearity Trims for Nyq1. Remember the sequence of programming the config files is Powerup_Analog_Config-->IL_Config_Nyqx_chA-->IL_Config_Nyqx_chB-->NL_Config_Nyqx_chA-->NL_Config_Nyqx_chB-->JESD_Config
0x400420,   //...
0x4002F9,   //...
0x6074F4,   //...
0x607501,   //...
0x6076EF,   //...
0x60770C,   //...
0x60780A,   //...
0x6079FE,   //...
0x608BF4,   //...
0x608C01,   //...
0x608DEE,   //...
0x608E0D,   //...
0x608F0A,   //...
0x6090FE,   //...
0x60A2F4,   //...
0x60A301,   //...
0x60A4EF,   //...
0x60A50C,   //...
0x60A60A,   //...
0x60A7FE,   //...
0x60B9F4,   //...
0x60BA01,   //...
0x60BBEF,   //...
0x60BC0D,   //...
0x60BD0A,   //...
0x60BEFE,   //...
0x60D0FF,   //...
0x60D100,   //...
0x60D2FF,   //...
0x60D301,   //...
0x60D400,   //...
0x60D500,   //...
0x60E7FF,   //...
0x60E800,   //...
0x60E901,   //...
0x60EA00,   //...
0x60EB00,   //...
0x60EC00,   //...
0x60FEFE,   //...
0x60FF00,   //...
0x4002FA,   //...
0x6000FF,   //...
0x600102,   //...
0x600201,   //...
0x600300,   //...
0x6015FF,   //...
0x601600,   //...
0x601701,   //...
0x601800,   //...
0x6019FF,   //...
0x601A00,   //...
0x602C00,   //...
0x602D00,   //...
0x603301,   //...
0x603401,   //...
0x400200,   //...
0x400300,   //...
0x400468,   //...
0x606800,   //...
0x001100,   //...
0x001204,   //...
0x005c87,   //...
0x001200,   //...
ADC32RFxx_LOWLEVEL
0x400200,   //JESD Interface Programming
0x400300,
0x400469,
0x600201,	// 14b mode and JESDMODE0 = 1 
0x700201,	
0x603700,	// PLL DIV mode = 20x
0x703700,
0x60323C,
0x70323C,
0x60333C,
0x70333C,
0x60343C,
0x70343C,
0x60353C,
0x70353C,
0x600180,	//set CTRL K
0x700180,
0x60070F,	//set K to 16
0x70070F,
0x001204,	// write 4 to address 12 page select
0x005600,   // sysref dis - check this was written earlier
0x005700,   // sysref dis - whether it has to be zero
0x002000,
0x002010    //Pdn sysref

  • 0 in reply to Bala Krishna E88
    TI__Genius 10705 points

    Hi Balakrishna,

    I have verified the config file on an ADC32RF45EVM connected to TSW14J56EVM at 2.5GSPS. I used SYSREF frequency of (2500/1024) MHz. 

    As 12.5GSPS is fairly high lane rate, you might have to adjust JESD swing and lane de-emphasis settings to get good eye margin. These settings can be adjusted using registers 

    JESD output swing: Register 03Dh (address = 3Dh) in Master Page

    Lane de-emphasis: Register 032h-035h (address = 032h-035h) in JESD Digital Page

    Regards,

    Vijay

  • 0 in reply to Vijayendra Varma Siddamsetty
    Prodigy 110 points

    HI,

    Problem not solved and we want to check our custom board with the least possible datarate.

    can you please send the configuration file for DDC Mode with 1 channel for the above requirement and clk & sysref frequency values,

    Thanks & Regards

    Bala Krishna

  • 0 in reply to Bala Krishna E88
    TI__Genius 10705 points

    Hi Bala Krishna,

    I will create a config file for a DDC mode with lane rate less than 5Gbps and test it on EVM before sharing with you. 

    I will send the config file by Friday. 

    Regards,

    Vijay

  • 0 in reply to Vijayendra Varma Siddamsetty
    TI__Genius 10705 points

    Hi Bala Krishna,

    Please find the ADC config file for Divide-by-3 real mode. This uses same JESD mode (LMFS = 8224) as the DDC bypass mode you want to use. But as divide-by-3 real decimation is used, lane rate rate will be divided by 3.

    Note that NCO is set to ~700 MHz.

    DDC_by6_real_8224_full_Ny1.cfg

    Regards,

    Vijay