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ADS7280 CONVST SIgnal

John Mladenik
Intellectual 280 points
Other Parts Discussed in Thread: ADS7280

I am interfaceing to the ADS7280 with an FPGA.    I had generated the CONVST signal looking like the timing diagrams in the data sheet insuranting the low time is greater than 50nS.    It was suggested tome that I should make the low time the whol conversion cycle and then just bring it high and then low right before the conversion which makes the CONVST signal look like the inverse of how you show it.   Is there a problem with doing it like this, any advanage or disadvantage to either way?

 

Also We are debating on the advantage and disadvantage to using tghe SCLK to drive the conversion.   If I use the internal Conversion the actualy sample is held on the falling edge of the CONVST so the value is syncronized to the CONVST signal no matter what clock is used as the conversion clock right? 

 

And

 

P33 of th spec mentions the quite zone.  Does this apply to all signals or only the CS?   Is it better to leave the SCLK off during the quiet zone?

 

thanks

John

  • 0
    TI__Guru**** 181091 points

    Hi John,

    You can certainly hold CONVST low for longer than the minimum 50ns, but to ensure there are no issues with acquiring the subsequent analog input sample, it should go high again before the end of conversion - please refer to Figure 2 on page 12 of the data sheet.  The CONVST input does in fact open the sample/hold switch regardless of using the internal clock or the external SCLK as the conversion clock.  Since you do not have access to the internal clock source, the actual timing of the EOC/INT output can dither +/- half a conversion clock cycle.  Using an external conversion clock to synchronize everything might be considered as an advantage in some applications.  The 'quiet zone' applies to all digital inputs - including the SCLK.  Best performance was seen when using a burst mode clock like you would find in a typical SPI interface.

  • 0 in reply to Tom Hendrick
    Intellectual 280 points

    Tom,

    Thanks so much for such a quick response.   I think I understand it now but a few more  questions comments.

    If the sample is held on the CONVST signal I see no advantage with respect to noise, that could possible happen with syncronizing CCLK to an external clock.   Using the SCLK to drive the conversion clock means you will have to drive the SCLK all the time and since the sample is held at CONVST it does not chance when the analog signal is held  by using the external SCLK to drive CCLK.  

    If the SCLK is always toggling and running at 42MHz  it would always infring on the "quiet zone" . And using the SCLK as the CCLK would not improve the syncronization of when the analog signal was held any better than using the internal CCLK.

    So for the best possible performance it would seem like using the internal sample clock while syncronizing CONVST to my external clks would give the best results.  

    If you agree then I plan to syncronize the CONVST with my system CLKs and power converters, but to use the internal CCLK for the conversion clock.  That way the SCLK is only toggling when the FPGA reads the data and I insure that when CONVST goes low is is when the SCLK is no toggling and system noise is at its lowest.  

    Also can I assume that there are absolutely no advantages to holding the CONVST low for most of the entire conversion period?   That I just need to insure that the low time meets the minumum requirement and then to bring it back high as shownin your timing diagram in the data sheet?

     

    thanks again for such a quick response.  

    John

  • 0 in reply to John Mladenik
    TI__Guru**** 181091 points

    Hi John,

    John Mladenik said:

    If you agree then I plan to synchronize the CONVST with my system CLKs and power converters, but to use the internal CCLK for the conversion clock.  That way the SCLK is only toggling when the FPGA reads the data and I insure that when CONVST goes low is is when the SCLK is no toggling and system noise is at its lowest.  

    I agree that this is the simplest way to interface to the ADS7280 - it simplifies the state machine a little as well I believe.  You may assume that there is no advantage to holding CONVST low for more than the minimum.  Using a fixed number of your system CLKs cycles such that CONVST = 0 for at least 50ns would be fine.  When you consider that the internal conversion clock has a potential span of 21 to 24.5MHz, the conversion is going to take at least 1.36us to complete.  You should bring the CONVST high before the ADS7280 goes back into sample mode.