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ADS127L01: ADS127L01 SCLK and FSYNC pins fan-out

Shaii Amrusi
Prodigy 160 points
Part Number: ADS127L01
Other Parts Discussed in Thread: LMK1C1108

Hello


1. Is it possible to cascade 6 ADCs (ADS127L01) in frame sync mode?
One frame sync master mode ADC outputs FSYNC (500 kHz) and SCLK (16 MHz) signals to 5 ADCs (and one FPGA) input pins, in frame sync slave mode. All the ADCs configuration pins are the same (OSR, FILTER). DVDD is 1.8 V. All the 6 ADCs share the same START signal. The shared CLK signal (16 MHz) is from clock buffer LMK1C1108.  F_DATA is 500 kHZ (OSR 32). I am afraid that due to the SCLK fan-out limit I may have problems. 
Is it possible?
If Yes, great!
If No, How many cascaded ADCs can be chained in that way?
2. Is there any way to work with 6 synchronized ADCs all in frame-sync master mode?
All the 6 share the same CLK, START, RESET, I expected all the FSYNC signals and SCLK signals will be the same. However, as far as I can see,  FSYNC signals are not in the same phase (SCLK signals are the same).
I can control the RESET and START edges in very high resolution (in time) from the FPGA if its necessary. Is it possible to work in that way?
3. In the data sheet of ADS127L01, 8.4.3 START Pin chapter:
" In frame-sync interface, DOUT goes low as soon as START is taken low, as shown in Figure 86 ".
I don't think it is correct. From what I see, when START goes low, DOUT is not constant zero. It becomes low when START goes back to high for a few cycles. 
Regards,
  • 0
    TI__Mastermind 36130 points

    Hello Shaii,

    You should be able to drive 5 ADS127L01 plus FPGA with a single ADS127L01, provided that the board capacitance is not too high and the devices are close together.  Each ADC digital input will have about 2pF of capacitance and the SCLK/FSYNC outputs should be limited to a total of about 20pF.  However, if you have long boards traces between the devices, then you could have signal integrity issues.  Since we do not have a specification for the maximum fanout, I would suggest adding a buffer to both the SCLK and FSYNC lines on the controller ADC to ease the driving requirements for this many ADC's plus the FPGA.

    Regarding your question 2, as long as you properly synchronize all ADC's, then the FSYNC and SCLK of each ADC will be aligned with each other. Figure 86 and Table 14 provide the timing requirements to achieve this operation mode.  

    Regarding question 3, there is a delay between START falling edge and DOUT falling edge.  However, we do not specify this, and it is not important to properly synchronize multiple devices.  After a SYNC, RESET, or MODE change in Frame Sync Mode, you should look for a low-to-high transition on DOUT to determine when data are fully settled.

    One other suggestion, as long as you can meet the timing requirements, it might be easier to use frame-sync slave mode for all ADC's and let the FPGA generate the SCLK and FSYNC waveforms.  In this case, most FPGA IO pins can drive a lot of capacitance, so you should not need any additional buffers.  Also note in Figure 104 of the datasheet that the DIN should be connected to ground instead of the FPGA.

    Regards,
    Keith Nicholas
    Precision ADC Applications