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DAC80004: Simple operation doubt and waveform

Abhishek P1
Prodigy 20 points
Part Number: DAC80004

Hi,

 

I am using DAC80004 for simple digital to analog conversion. LDACbar and POR pins are connected to 0V. Digital data entered using SDIN,SCLK,SYNC pins and output measured at VoutA only. Does this work with LDACbar and POR pins connected to 0V.??

 

Which command needs to be used for simple data conversion. Are there sample waveforms to illustate the command structure.

  • 0
    TI__Mastermind 34098 points

    Hello,

    POR can be connected to GND or VDD. Connecting POR to GND powers up the DACs to zero scale and VDD powers up all DACs to midscale. /LDAC can be held at GND if the device is set up in synchronous mode, or asynchronous mode when using the software /LDAC. In synchronous mode, the DAC will be updated on the falling edge of the 32nd SCLK. The commands will be as follows:

    Synchronous mode:

    • LDAC register: 0x06000001 (puts DAC channel A in synchronous mode, ignores /LDAC pin)
    • Write to buffer A: 0x000XXXX0 (XXXX is 16-bit buffer data, DAC output will be updated on falling edge o 32nd SCLK)

    Asynchronous mode + software /LDAC:

    • Write to buffer A: 0x000XXXX0 (XXXX is 16-bit DAC data)
    • Update DAC A: 0x01000000 (updates DAC channel A output with data in buffer)

    An example timing diagram is provided in the datasheet:

    The /LDAC(1) line is for asynchronous operation using a hardware /LDAC, you'll be using the software /LDAC

    The /LDAC(2) line is for synchronous operation

  • 0 in reply to Katlynne Jones
    Prodigy 20 points

    Hi Katlynne,

    Thank you for the explanation.

    I had one more doubt after reading the datasheet. The analog voltage will be seen on VoutA pin at the end of 32nd clock cycle right? What role does CLRB pin play here, I have connected CLRB pin to 0V for simpler operation. Does this impact on controlling when the output will appear on VoutA pin?

    Thanks,

    Abhishek

  • 0 in reply to Abhishek P1
    TI__Mastermind 34098 points

    Hi Abhishek,

    The clear pin works as follows:

    A falling edge on the clear pin will clear the DAC outputs to zero, mid scale, or full scale. Because the pin is falling edge sensitive, holding the pin at 0V should have no effect on the output. 

    Are you referring to the statement "The device exits clear mode on the 32nd falling edge of the next write to the device"? This is only relevant if a low pulse (high-low-high) is applied to the CLR pin, which will put the DACs in clear mode. The device will exit clear mode on the next write cycle.

    Let me know if you have any further questions!