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ADS131A02: DRDY pulse after RESET before write register

Shota Mago
Expert 8110 points
Part Number: ADS131A02
Other Parts Discussed in Thread: ADS131A04

Hi team,

My customer uses ADS131A02 with Asynchronous Interrupt Mode and he is asking questions about DRDY behavior after RESET.

After both hardware/software reset, DRDY pin shows some periodic pulses as shown in ① and ② in this waveform which can be accessed via TI network.

  1. Is this expected behavior?
  2. Is there no possibility that DRDY sticks to High or Low after Reset?

[Background of the questions]

As I mentioned above, the customer uses the device with Asynchronous Interrupt Mode. So he designed that master controller doesn't output SLK unless IQR is interrupted. Current device setting procedure is as follows.

  1. Power Up
  2. Hardware or Software Reset
  3. Wait 7ms
  4. Output SCLK from controller once falling of DRDY is received. 
  5. Receive READY word and send UNLOCK command

As of now, the customer uses DRDY pulse to trigger SCLK from controller and it works properly without any problem so far.

But he is concerned about if there is possibility that DRDY sticks to High or Low and controller never output SCLK because there is no description about DRDY behavior after POR on the datasheet.

Should he just output SCLK after 4.5ms from RESET w/o triggering?

Best regards,

Shota Mago 

  • 0
    TI__Guru 55152 points

    Hi Mago-san,

    Our primary support for this device is out today, so I would like him to double-check my response once he returns. 

    I believe this is expected behavior. Looking at figure 69. in the datasheet, you can see that there are periodic pulses in the data frame. It appears that there is only one pulse for ①, but if you look near the cursor I believe a second pulse can be seen - similar behavior as ②.

    As 9.5.3.2 RESET: Reset to POR Values says, after issuing a RESET, the device enters a default state - which I believe should be consistent. No possibility of sticking high or low. 

  • 0 in reply to Alexander Smith
    TI__Expert 8110 points

    Hi Alex-san,

    Thanks for your comment.

    As for Figure.69, is DRDY pin behavior correspond to pulses of Data Frame on Figure.69?

    If so, are some pulses expected on DRDY pin after HW/SW reset w/o SCLK from master?

    I can wait for double checking with primary supporter of this device.

    I appreciate your support.

    Best regards,

    Shota Mago

  • 0 in reply to Shota Mago
    TI__Guru 55152 points

    Hi Mago-san,

    I believe so. DRDY typically pulses to show that the device is functional. 

    Let's wait for Ryan to return to confirm, he will be back on Monday. 

  • +1 in reply to Shota Mago
    TI__Guru 66256 points

    Hello Mago-san,

    The Data Frame signal at the top of Figure 69 is essentially the /CS input from the host. When Data Frame is low (/CS = 0), the interface is enabled.

    /DRDY was not intended to be used as an indication of when to communicate with the device. Following the POR, the host is expected to send the NULL command in consecutive frames (i.e. to poll the device) until the READY response word is received. After unlocking the device, the customer will need to enable the ADCs and reconfigure the device register settings.

    I think the most robust method is to send the NULL command after ~4.5 ms following the reset.

    Regards,

  • 0 in reply to Ryan Andrews
    TI__Expert 8110 points

    Hi Ryan-san,

    Thank you for your reply.

    I will ask the customer to send NULL command 4.5ms after reset.

    Let me ask you another small question.

    What is the behavior of the DRDY pin until 1st null command is accepted after reset?
    Does it work at a certain default periodic signal, or does it become unstable(not defined) until the configuration command is accepted?

    Best regards,

    Shota Mago

  • 0 in reply to Shota Mago
    TI__Guru 66256 points

    Hi Mago-san,

    I will try to check this behavior on the EVM tomorrow.

    Regards,

    Ryan

  • 0 in reply to Ryan Andrews
    TI__Expert 8110 points

    Hi Ryan-san,

    Noted.

    Thanks for your support as always.

    Best regards,

    Shota Mago

  • +1 in reply to Shota Mago
    TI__Guru 66256 points

    Hello Mago-san,

    The ADS131A04 will power-up with the default register settings. The DRDYn pin will pulse low at the default data rate of 640 Hz before sending any SCLKs to the device.

    Best regards,

    Ryan

  • 0 in reply to Ryan Andrews
    TI__Expert 8110 points

    Hi Ryan-san,

    Thank you so much for confirming behavior of DRDY using EVM!

    Best regards,

    Shota Mago