DS90ub941/DS90ub948 display flickly

Hi Chungfeng,

Normally, if there is a flickering issue, most likely is related to timing issue. I would like to isolate the 8155 first. Have you try with 941 patgen? If yes, did you see similar problem?

Aaron

Dear Aaron,

Thanks for your reply. 

I have tried 941 test pattern. If set 0x44 to reg 0x65 , the flicker is not exist.  If set 0x40 or 0x4C to reg 0x65, the flicker is exist.

And i have tried to change the porch of panel too, the issue is only exist.

But if we used the ser/des from maxim ,  the other configure is the same, the issue is not exist.

Thanks!

Chunfeng

Hi Chunfeng,

Normally, the patgen should work with internal or external clock. Since you are using the external clock for your reference clock, you need to make sure that you set to continuous mode for 941AS and your SoC. I think this could be something related to timing issue. Does the patgen PCLK match the panel requirement? Can you share the panel datasheet?

Hope this helps. Let me know if you have further questions.

Aaron

Dear Aaron,

Sorry , I'm later.

And I am sure that I set to continuous mode for  941 and SoC.  I have tried some timing. example:

qcom,shared-display-base-mode {
qcom,mode-h-active = <1920>;
qcom,mode-h-front-porch = <120>;
qcom,mode-h-pulse-width = <48>;
qcom,mode-h-back-porch = <88>;
qcom,mode-h-active-high;
qcom,mode-v-active = <720>;
qcom,mode-v-front-porch = <8>;
qcom,mode-v-pulse-width = <2>;
qcom,mode-v-back-porch = <5>;
qcom,mode-v-active-high;
qcom,mode-refresh-rate = <60>;
qcom,mode-clock-in-khz = <95961>;  // PCLK
};

or:

qcom,shared-display-base-mode {
qcom,mode-h-active = <1920>;
qcom,mode-h-front-porch = <40>;
qcom,mode-h-pulse-width = <10>;
qcom,mode-h-back-porch = <30>;
qcom,mode-h-active-high;
qcom,mode-v-active = <720>;
qcom,mode-v-front-porch = <10>;
qcom,mode-v-pulse-width = <5>;
qcom,mode-v-back-porch = <5>;
qcom,mode-v-active-high;
qcom,mode-refresh-rate = <60>;
qcom,mode-clock-in-khz = <88800>;  //PCLK
};

and so on. but the issue is only exist.

I want to upload the panel datasheet, but the max size is limit.

Thanks!

chunfeng

Hi Chunfeng,

I will review this, and get back with you tomorrow.

Aaron

Hi Chunfeng,

Thanks for sharing the resolution. Based on the timing, this shouldn't be an issue. I think we need to look into the SI performance of the incoming DSI clock as you used it as external clock source for the reference clock. Is there a way for you monitor the DSI clock? I would like to see the jitter tolerance.

Aaron

Dear Aaron,

Sorry, for me, now the only way is meansure the waveform with oscilloscope. I have no other way to monitor the jitter tolerance.

Can way adjust the registers of 941/948 to match the jitter?

Thanks!

Chunfeng 

Hi Chunfeng,

As far as I know, there is no register to set the jitter. We have the jitter tolerance in the datasheet that we must meet the threshold. This is why I am asking to take the measurement so that we can see clearly.

Aaron