ADS127L01: ADS127L01 SCLK and FSYNC pins fan-out

One frame sync master mode ADC outputs FSYNC (500 kHz) and SCLK (16 MHz) signals to 5 ADCs (and one FPGA) input pins, in frame sync slave mode. All the ADCs configuration pins are the same (OSR, FILTER). DVDD is 1.8 V. All the 6 ADCs share the same START signal. The shared CLK signal (16 MHz) is from clock buffer LMK1C1108.  F_DATA is 500 kHZ (OSR 32). I am afraid that due to the SCLK fan-out limit I may have problems. 

Is it possible?

If Yes, great!

If No, How many cascaded ADCs can be chained in that way?

2. Is there any way to work with 6 synchronized ADCs all in frame-sync master mode?

All the 6 share the same CLK, START, RESET, I expected all the FSYNC signals and SCLK signals will be the same. However, as far as I can see,  FSYNC signals are not in the same phase (SCLK signals are the same).

I can control the RESET and START edges in very high resolution (in time) from the FPGA if its necessary. Is it possible to work in that way?

3. In the data sheet of ADS127L01, 8.4.3 START Pin chapter:

" In frame-sync interface, DOUT goes low as soon as START is taken low, as shown in Figure 86 ".

I don't think it is correct. From what I see, when START goes low, DOUT is not constant zero. It becomes low when START goes back to high for a few cycles. 

Regards,

Shai Amrusi