Hi,
I've two cases here. Case 1 in which I use a ADC12DJ5200RFEVM with Stratix 10 TX evaluation kit and in Case 2 custom ADC board with the Stratix 10 TX evaluation kit. The mode of operation is JMODE 31. The test pattern data fed is short transport test pattern. CRC12 is selected on both ADC and FPGA IP core. JESD204C link is up and is always stable.
Case 1: In the signal tap I notice that many bits received are corrupted but there's no crc or parity errors.
Case 2: In the received test pattern one or two bits gets corrupted randomly and there are CRC errors. (Parity errors were corrected by enabling pre emphasis)
I would like to know for case 2 what might be causing the CRC errors and how to tackle it. (Custom board worked fine with JESD204B).
P.S.: Same behavior was observed with ramp test pattern too.
