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ADS1262: Could you please review my board containing two ADS1262 chips?

Patrick Coffey
Prodigy 165 points
Part Number: ADS1262

I’d very much appreciate a design review before I send a datalogger board I’ve laid out for manufacturing.  I’ve marked areas where I’m uncertain of my design decisions.

The board that employs two ADS1262 chips.  It’s a Raspberry PI daughter board that serves as a slave on two separate SPI buses.  It will acquire data at 100SPS on four differential inputs at 100SPS, two on each channel.  The board also incorporates a 256KB EEPROM.  I’m running the SPI buses entirely through commands, so I haven’t connected RESET, PWDN, etc. 

The board draws 3.3 and 5V power from the Pi, so I haven’t worried much about fuses, etc. I’ve checked the 5V and 3.3V power from the PI, and there’s about 7m rms noise on both, mostly 60Hz.  AINCOM, 5V, 3.3 BYPASS, REFOUT are connected through a 1uF capacitor to ground.  AVDD = 5V, DVDD = 3.3V, AVSS = DGND = GND.

It’s a 4-layer board:  Component – Ground (single ground plane, no traces) – Power (both 3.3V and 5V) – Signal for traces that I couldn’t connect without vias on the Component plane.

I Imitated the ADS1262X-EVM for layout and for analog input filters and, tried to follow advice in ADS1262 datasheet on layout.  Because the data rate for my board is only 100 SPS, I’ve swapped the 47nF capacitors on the EVM’s input filters for 10uF, giving a calculated cutoff frequency of 338Hz.  Please comment on this.

The two ADS1262 chips are separated physically, each the only device on separate SPI buses, so CS is tied to GND for both chips.  All unused inputs on the two ADC’s are also tied to ground.  I’ve used one layer for both analog and digital components but have separated them, analog at the bottom, digital on top. 

I have separated the differential inputs but have not worried too much about exactly matching  trace length because of the slow sample rate.  Please comment on this.

I’m using the chips’ internal clocks and reference voltages.   Because of the slow sample rate, I intend to run the clock at 250KHz or so.  All digital SPI signals (SCLK, MISO, MOSI, DRDY) include 47ohm resistor to minimize ringing.  SCLK, MISO, and MOSI don’t pass through vias.  DRDY does but same info is largely redundant as same info is contained in MISO.  AINCOM passes through a via.  One pair of CAPP signals passes through vias, other is direct. 

Both chips' CAPP and CAPN signals are connected by a 47nF capacitor and brought out to a connector.

I used 0.400 mm traces throughout for signals, 1mm for power and GND wherever possible.  Please comment on this.

All four copper planes are tied to ground, but I have dropped multiple vias to the ground plane from the Component plane wherever possible, several vias to the Power plane around connections, stitching through-board vias in multiple places to reduce inductance.  Please comment on this.

The two ADS1262 chips require 3.3 V and 5V, and the EEPROM requires 3.3V. Power is dropped from Component plane to Power plane through two vias, then run to vias up to the Component plane.  Please comment on this.

I'm happy for our conversation to be public but not schematics, photos, gerbers, etc.  I develop in Kicad.  What files would you like?

Thanks for your help.

 

  • 0
    TI__Guru 51846 points

    Hi Patrick,

    A few comments/questions below, but nothing significant. In general it seems like you have followed best practices very well, and I cannot foresee a reason why anything you've discussed in this post would cause problems:

    • The CAPx pins need a 4.7nF capacitor (C0G type), not 47 nF. Make sure that this capacitor is as close to the ADC pins as possible. I was also not sure why you had these pins brought out to a connector. There is likely no need to modify this capacitor value, in fact changing the value of this capacitor has caused issues in other customer's systems.
    • For the differential filter cutoff frequency, consider the time it takes for the inputs to respond to a step change. If the cutoff frequency is very low, it will take 12-15 time constants to settle to a final value (at the 20+ bit level), so that might be something to consider depending on the types of inputs you intend to measure and how quickly they might change
    • In general I would recommend symmetric layouts for the input signals, or as close to it as possible, just to avoid any issues that might arise from this. But if they are pretty similar then it should be okay. As long as you don't have one input directly connected and another input connected with a set of vias and traces that look like spaghetti
    • Not having access to CS, RESET, or PWDN could make recovering from a digital communication issue challenging. Specifically being able to reset the SPI interface, as a RESET command might not be read properly if there are issues with the SPI communication. There is an autoreset function in the ADS1262, described in 9.4.4.5, that could be used in this case, but it needs to be enabled in the INTERFACE register. Again, something to consider
    • No comments on the questions about trace length or power, looks good

    -Bryan