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ADS8166: SPI Read/Write Problems of Register

Cedrick
Expert 8270 points
Part Number: ADS8166

Hi,

Good day.

Our customer is using the ADS8166 and they have the following question.

"With the register readout procedure described in the datasheet. I cannot readout any of the registers. I use a Raspberry Pi with spidev. The readout for register address 0x00 looks like this:
spi.xfer2([0b00010000;29;0x00]) #read command
data=spi.xfer2([0b00010000;29;0x00]) #should not matter what to send here according to datasheet
what i would expect would be the 8bit Register Data followed by two zero bytes.
What i get is two bytes (ADC value) followed by a zero byte.

However it is possible for me to change the ADC Channel with spi.xfer2([0b00001000,29,1])
I tested this with fixing one of the inputs to GND another one to a fixed voltage and getting data from both alternating between them. -> MOSI Line works and MISO as well
I hooked up a logic Analyzer to the system but it just verifys the data i get with the Rpi.
Because this write command worked I tried to blindly put the device in the debug mode. (Write the REG_ACCESS_BITS in the Reg Access Register and write 0x01 to Data_CNTL_Reg 0x10 to enable debug mode) but this failed as well and the ADC just gave me more 16 bit Data which was different from the debug value.

I checked the second SDO Line with the Logic Analyzer as well but it stays LOW all the time so is deactivated as expected.

Is there something I am missing to get Read Access to Registers?
Is there something missing to get Write Access to the Write Access Register or any other Register except for the Chan Id Register?
Do I need to stop the 16bit ADC Data Output before i can read Register Values?
If so how can I Stop the output? I already tried to powerdown the adc module but this failed as well.
Is there some special frequency I need to use? I tried 400000Hz 800000Hz 1600000Hz already
Do I need some special breaks/Read more bytes? Already tried    burstread 6 bytes spi.xfer2([0b00010000,29,0x00,0b00010000,29,0x00]) Got [ADC_MSB;ADC_LSB; 0x00, 16,29,0]->just got back my message of the first three bytes after the usual frame."

We would appreciate your inputs on this matter. Thank you.


Regards,

Cedrick

  • 0
    TI__Mastermind 36240 points

    Hello Cedrick,

    Please ask the customer to provide an image of the SPI bus capture during the READ REGISTER.  It should look similar to the below diagram:

    Also note that a read register command requires to transfer frames, where frame 1 is the RD_REG command, and in frame 2, you get the contents of the 8b register followed by 16 zeros.  For all other commands, including NOP (no operation, all zeros) you will get the conversion result.

    There is no command to stop a conversion.  If you send a Read Register command, the converter will still convert but the output will be replaced by the 8b register value.  You do not need to write to any registers first to read a register value.  In order to write to the configuration registers Addresses 04h through 11h, you must first write AAh to the REG_ACCESS register at address 00h.

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • 0 in reply to Keith Nicholas
    TI__Expert 8270 points

    Hi Keith,

    Good day. Thank you for your support.

    Here are the capture of the bus.


    The Logic Capture shows a write to Register 0x00 with the Register Access Command and afterwards the read of Register 0x00. The Last Frame should contain the Data (170) of Register 0x00 and is at the same time another read command of the Register 0x00. I attached a closeup of the Read Command as well to show bit alignment (Cpha=0 Cpol=0) and the Clokck Frequency of 400khz. The Low State of the CS Line between two accesses is not intended but can t be prevented in Code. (Looks like a sideeffect of the combination of Logic Analyzer Rpi and spidev because it shows up for other spi devices as well).


    Regards,

    Cedrick

  • 0 in reply to Cedrick
    TI__Mastermind 36240 points

    Hello Cedrick,

    The problem is with the extra /CS low pulse between frame 1 and frame 2 of the read command.  The results of the register read are loaded into the ADS8166 output register on this /CS low transition.  Since no clocks are issued, it interprets this frame as a NOP, and then in the next frame, it outputs the next conversion data result.

    The customer needs to figure out how to eliminate this extra /CS pulse in order to get the register read operation to function correctly.  If necessary, they can always control /CS with a GPIO line.

    Regards,
    Keith