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ADS1261: Delay time after register write

Part Number: ADS1261

Dear Sirs

After setting the gain and input mux, is there a wait time before I can start a conversion with the start pin or can I start the conversion immediately after returning from the register write function? 

  • Hi Dennis,

    Did you intend to use pulse convert mode or continuous conversion mode?

    Conversions automatically restart after PGA and INPMUX registers are successfully written to, so this should not be an issue if you are just holding the START pin high.

    Please provide a few more details on how you want to take data so we can help make sense of what to expect here.

    -Bryan

  • Bryan

    I'm running in continuous mode.  At the moment, I'm putting a 1ms delay between the register write and the start.  It sounds like I don't need to do this.  After the start, I wait 3ms for the external and SINC filters to settle.  I'm acquiring three differential channels.  That's why the 3ms wait time.  I'm not using the DRDY pin for data ready acknowledgement. I just go and get the latest data after the 3ms.  Sample rate is 7200sps and the filtering is SINC3.  This results in a .841ms latency.  Your thoughts. 

  • Hi Dennis,

    So right now the flow is:

    • WREG (CH1) --> wait 1ms --> set START high --> wait 3ms --> RDATA --> WREG (CH2) --> wait 3ms --> RDATA --> etc.

    Is that accurate? Since you are holding START high, it was not clear to me if you are waiting 1ms after each time you send a WREG command or only during the initialization procedure. In either case, this delay should not be necessary, especially if you are holding START high in continuous conversion mode

    I would encourage you to use the DRDY signal if possible to determine when data is ready. I recognize that you are allowing considerable time to pass from the WREG to polling data, but there would always be some concern that misaligned clocking could, over time, cause errors and lead to unexpected data (I have seen this issue with other customers who try to "time" the output data correctly). Also, it seems odd to set the output data rate at 7200 SPS (0.841ms latency) while your actual output data rate is closer to 333 SPS (3 ms). Using DRDY would allow you to get data out at the 0.841ms conversion time.

    -Bryan

  • Bryan

    I understand about

  • Bryan

    Sorry about that.  As I was saying, I understand  the misaligned clocking.  I'm sorry I'm not being clear on my procedure.  It is as follows: 

    WREG (CH1) --> wait 1ms --> set START high --> wait 3ms --> set START low --> RDATA --> WREG (CH2) --> wait 1ms --> set START high --> wait 3ms --> set START low --> RDATA --> etc.

    That being said, the above procedure is for long term testing of some high precision pressure sensors.  This testing will run for 5 to 6 months.  In the end we will be using these sensors in a control process.  In that process, the control loop time will be 1ms.  That's why I'm running the sampling rate at 7200sps.  In addition, I will be using the DRDY in an ISR to service the data read.  I'm trying to carve out as much dead time as possible.  That's why the inquiry into the wait time between the register write and the start but that doesn't seem to be a problem now.  Therefore, my control loop process would be,

    WREG(chn1(PGA,INPMUX)) ---> set START high ---> wait for DRDY ---> RDATA ---> WREG(chn2(PGA,INPMUX)) ---> wait for DRDY ---> RDATA --->etc.  

  • Hi Dennis,

    Thanks for the additional explanation, this makes sense.

    And the flow you have at the bottom of your post makes sense to me for the most reliable system.

    Let me know if you have additional questions on this topic. Or feel free to start a new thread if they are unrelated to this specific topic.

    -Bryan

  • Thank you for your patience.