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ADS5407EVM: ADC input microstrip

user4166923
Prodigy 100 points

Part Number: ADS5407EVM

Hi,

I am looking at the design files for the ADS5407EVM evaluation module (for the ADS5407 family of ADCs). I noticed that the board layer stack indicates the stack being 10 layers all with FR4 thickness of 8 mils. According to any online microstrip calculator, it would indicate for 50ohms, you need tracks of ~14mils, yet the design has been done with 20 mil tracks. Also, the differential lines are 7.5 mils and the outputs (LVDS) that feed into an FPGA (e.g.) are 5 mils. Now ordinarily, I would say 14 mils is not far from 20 but I am wondering what is the thinking behind this. I am designing a board that is 12 layers with 6 mil FR4 height, so normally a 50ohm track is 10 mils. I would like to know this because it relates to how I lay out the board and the tracks I use. This is my input circuit so far. Any comments welcome.

  • 0
    TI__Expert 5430 points

    Hello,

    So that particular design has a stackup that was designed by the vendor.  The material used in the EVM is not FR4 but is Nelco N4000 which has a different dielectric constant than FR4.  If you use FR4 your stackup thicknesses will be different and need to be determined based on your particular requirements

    If you were looking at the Allegro files, the default within the tool itself is 8 mils and shouldn't be used as a guide.  The copper layers are all 1/2oz with the layer thicknesses as follows:

    L1
    6.1
    L2
    4
    L3
    7.9
    L4
    4
    L5
    7.9
    L6
    4
    L7
    7.9
    L8
    4
    L9
    6.1
    L10
  • 0 in reply to Geoff Roth
    Prodigy 100 points

    Oh that is confusing in Allegro. Thanks this is very helpful.  Although even if I assume er ~3.5 for Nelco N4000 and a height of 6.1 mils for the top layer, it gets me 38 ohms for a 20 mil track.  The change in er, has little effect here in this range.