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Original question:

ADS4449: ADS4449 High-Resolution Mode and DC-Offset

ADS4449: ADS4449 High-Resolution Mode and DC-Offset (continued)

Markus Haag
Prodigy 140 points
Part Number: ADS4449

Hello,

it has been a while since the last post in the thread related to this one (see title above). have you found out more about the issue in the meantime?

Best regards

Markus

  • 0
    TI__Guru* 91947 points

    Markus,

    Can you apply a full scale signal (say -1dBFS, 10MHz, sinewave) and check if offset still varies?

    How many time domain samples are you processing to compute offset? Can you send the time domain output data of ADC?

    This will help design with trouble-shooting this issue.

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 140 points

    Hi Jim,

    ok, doing new experiments will have to wait until Monday. However, I can try answering your other question in the meantime. Maybe these information are useful.

    The ADC startup routine runs when no signal is applied to the ADC. In all of my recent measurements the inputs of the ADC were at 0V (i. e. differentially; of couse, the common-mode voltage is as defined by the according bias output pin of the ADC). In all scenarios, 32768 samples were recorded at a rate of 240 MSa/s. Except for noise, the signal from the ADC was a straight horizontal line located up to +/-200 mV away from zero. Multiple recordings were taken minutes or hours later and still resulted in a straight line at the same location away from zero.

    By turning the high-SNR-feature off and back on again, the position of the line changed (randomly, as it seems).

    In January I played around with turning the high-SNR feature off and on until I had a situation with a large offset (+200 mV). In this case, I did apply a full-scale sine wave. The result was clipped at the digital code +8191 and not clipped in the negative range. After further increasing the peak-to-peak amplitude of the input signal beyond "full-scale plus 2 x offset", it could be shown that clipping occurs at codes +8191 and -8192 independently of the offset.

    Using a 1 MHz triangular waveform and varying the amplitude it seemed to me as if inside the ADC the signal had a few more MSBs (and some offset) and that it is clipped to the fixed output range of -8192 ... +8191 right before it is sent to the LVDS lanes.

    Unfortunately, I didn't save any data in January, so I will have to redo the experiments. When I'm doing this, I will also add one test in which I try to apply the full-scale signal before the startup-routine begins.

    Regards,

    Markus