ADS1283: ADS1283 collect data question

Hi Zhonghui,

In regards to your questions...

1. The input signal is over-sampled at the modulator clock frequency and then is post-processed by the digital (FIR) filter. The sampling rate is fixed for all data rates, but the decimation ratio will be different for each output data rate. Changing the the filter data rate will change how many samples are "averaged" and also the delay time from when the input is sampled to when you can read the result will be different. However, signal phase is not affected by the output data rate.
   
   Depending on whether you select the linear phase or minimum phase FIR filter, the minimum phase filter may introduce some distortion to the signal as the group delay is not constant over frequency for the minimum phase filter, as it is for the linear phase filter (See Table 42).
    
   
   
2. Are you asking about how to synchronize multiple ADCs to ensure that they are synchronously sampling? ...To do this you would need to ensure that the same clock signal is provided to each ADC (on the CLK pin) and then you would need to synchronize all of the devices simultaneously (by issuing a rising edge pulse on the SYNC pin to all devices at once).
   
   NOTE: That there is one important timing restriction on the SYNC pulse. The SYNC rising edge should not be within 30 ns of the CLK rising edge. I would recommend using a flip-flop to re-clock the SYNC's rising edge so that it aligns with the falling edge of CLK, if using GPIO signal to control the SYNC pin.
   
   Additionally, if you have a GPS clock, then you could consider using it to drive the SYNC pin and operating the ADS1283 in continuous-sync mode. This will ensure that ADCs get re-synchronized if the CLK signal drifts with respect to the GPS clock. However, this is usually not required if you can share a single CLK source between all ADCs in your system. Continuous sync mode more beneficial in a distributed system where multiple CLK sources are required.

I hope that answers you questions. Let me know if it doesn't or you you have any additional questions.

Best regards,
Chris

Hi Zhonghui,

When writing to the device's configuration registers (for example changing the device data rate), the ADC will start a new conversion after the WREG operation. Initially, this new conversion will be out-of-phase with the previous data rate since the continuous conversions are interrupted and the new conversion begins on a different CLK edge.

However, if you were using continuous-sync mode and changed the device data rate, the next GPS SYNC pulse would force the ADC conversions to re-synchronize to the GPS clock. Yes, there would be at least a 63 conversion period delay between conversion results, but the ADC will eventually resume conversions on the same CLK edge as before.

• As for formulas, take a look at Table 12 in the datasheet. The SYNC clock just needs to be an integer multiple of the data rate, but it does need to occur within the exact CLK period in order to avoid unnecessarily re-synchronizing the ADC. The relationship between fDATA and fCLK is: fDATA = 4 * N, where N is the decimation ratio given by Table 8.
  
  
• Additionally pay attention to the the last paragraph on Page 33 of the datasheet which describes a required command sequence after the WREG operation to re-establish synchronization.

Best regards,
Chris