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ADS1231: /DRDY&DOUT Output

Zeming Kong
Expert 3515 points

Part Number: ADS1231

Hi team,

Could you tell me what the output of /DRDY&DOUT will be if SCLK stays in L state?

Data ready signal will be generated every tCONV period, but DOUT will be L? or /DRDY&DOUT all stay in L state if SLCK is L?

Best,

Zeming

  • 0
    TI__Guru** 113765 points

    Hi Zeming,

    The DRDY/DOUT pin will hold the last value transmitted from the device when it is read.  At the end of the conversion, the DRDY/DOUT pin will transition high to low to signal the conversion is ready to be read from the device.  If the DRDY/DOUT is low from the last read then DRDY/DOUT will toggle low to high to low at the end of the conversion.  This transition is shown in Figure 19 of the ADS1231 datasheet as tUPDATE.

    I generally recommend setting the DRDY/DOUT signal to both the SPI input as well as a GPIO (2 connections on the micro) where the GPIO input can be used as a falling edge interrupt.  The pin can also be polled for a low state if the DRDY/DOUT pin is forced high by sending extra clocks.  Forcing the pin high is shown in Figure 20.

    Best regards,

    Bob B