Because of the Thanksgiving holiday in the U.S., TI E2E™ design support forum responses may be delayed from November 25 through December 2. Thank you for your patience.

  • State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 46 subscribers
  • Views 279 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DAC38RF84: Setup issues / 6x, 8x interpolation support on DAC38RF84

Dan Abbey
Prodigy 590 points
Part Number: DAC38RF84

Hi Team, 

Could you please check the below customer error codes to make sure i'm 100% correct. Customer is evaluating DAC38RF84, and is testing using LMFSHd = 82121, interpolation 6x, 8x. From table 44 of the datasheet this configuration is not supported so i believe this is causing the error codes and they need to move to the RF80. 

Error codes below: 

"DAC A, Lane 0 code synchronization error"

"DAC A, Lane 0 8b/10b not-in-table code error"

"DAC A, Lane 0 8b/10b disparity error"

"DAC A, Lane 0 read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialize with mem_init_state)"

"DAC A, Lane 1 code synchronization error"

"DAC A, Lane 1 8b/10b not-in-table code error"

"DAC A, Lane 1 8b/10b disparity error"

"DAC A, Lane 1 read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialize with mem_init_state)"

"DAC A, Lane 2 code synchronization error"

"DAC A, Lane 2 8b/10b not-in-table code error"

"DAC A, Lane 2 8b/10b disparity error"

"DAC A, Lane 2 read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialize with mem_init_state)"

"DAC A, Lane 3 code synchronization error"

"DAC A, Lane 3 8b/10b not-in-table code error"

"DAC A, Lane 3 8b/10b disparity error"

"DAC A, Lane 3 read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialize with mem_init_state)"

"DAC A, Lane 4 code synchronization error"

"DAC A, Lane 4 8b/10b not-in-table code error"

"DAC A, Lane 4 8b/10b disparity error"

"DAC A, Lane 4 read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialize with mem_init_state)"

"DAC A, Lane 5 code synchronization error"

"DAC A, Lane 5 8b/10b not-in-table code error"

"DAC A, Lane 5 8b/10b disparity error"

"DAC A, Lane 5 read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialize with mem_init_state)"

"DAC A, Lane 6 code synchronization error"

"DAC A, Lane 6 8b/10b not-in-table code error"

"DAC A, Lane 6 8b/10b disparity error"

"DAC A, Lane 6 read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialize with mem_init_state)"

"DAC A, Lane 7 code synchronization error"

"DAC A, Lane 7 8b/10b not-in-table code error"

"DAC A, Lane 7 8b/10b disparity error"

"DAC A, Lane 7 read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialize with mem_init_state)"

Additionally, i think there's an error in the datasheet which has caused the customer to select the wrong device. On Page 6 the overview states the RF84 can support 6x interpolation, but in table 9 P44 there is no option for the RF84 with 6x interpolation. Can you please check and confirm table 44 is correct. 

Thanks and best regards, 

Dan

  • 0
    TI__Guru* 91947 points

    Dan,

    Looking at Table 9 on page 44, you will see that the first row calls out 6x interpolation for 82121 mode. This is a valid mode for the DAC38FR84 device. I think the customer is having an issue with the clock frequencies between the FPGA and DAC or incorrect register settings. Please ask for the following info from them:

    DAC sample rate

    FPGA data rate

    SYSREF rate

    K setting

    Is the DAC using PLL mode or external clock mode?

    Based on this info we can send a working configuration file they can compare to their DAC register settings. 

    Regards,

    Jim

  • 0 in reply to jim s
    TI__Prodigy 590 points

    Thanks Jim, i'll ask the customer for the further info, 

    I'm still a bit confused by table 44, doesn't the lack of a tick in the box signify that 6x interpolation isn't supported? what does the tick mean if the blank entries are also supported? 

    BR

    Dan

  • +1 in reply to Dan Abbey
    TI__Guru* 91947 points

    Dan,

    I missed that part. This is definitely an error in the data sheet and will be corrected in the next release.

    Regards,

    Jim 

  • 0 in reply to jim s
    TI__Prodigy 590 points

    Thanks Jim, 

    Thats great news, much easier to fix than a board rework. I've sent the config files you provided across to the customer, I'll mark this thread as resolved