Hello.
I have problem with ADS 1282. CLK - 4 MHz. Scheem connceted ADC as fig.40 in the datasheet.
DRDY pin work not well. It`s never goes to low.
I have next figures: 1- SCLK, 2- Dout, 3 - DRDY pins
This is pictures like fig 30 in datasheet ADS1282 page 21.
I try work in continius mode (by default). I uderstad that DRDY must be high and then new data ready it goes to low. I can`t see it
What i do wrong?
Thank a lot for help