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TSW3100 and DAC5682

Michael S.
Prodigy 10 points
Other Parts Discussed in Thread: DAC5682Z, CDCM7005

Hello,

I am using the TSW3100 to generate a single sinusodial tone with 50MHz
via the DAC5682Z Evaluation Module. I use the multitone software
(version 1.0) which was delivered with the TSW3100 board to generate
this signal, and an external clock signal of 1GHz, 13 dBm (1 Vrms for 50
Ohm). For the DAC Board settings, I utilized the sample configuration
files delivered with the software: Example_2.reg7005 for CDCM7005 and
Example_2.reg5682 for the DAC6582Z (single DAC, 2x interpolation). The
board is in its default configuration (jumpers) and the only thing I
have changed are the 4 resistors you need to uninstall (R137, R156,
R153, R155) and I installed R134, R109, R155, R156 instead to measure
directly the DAC output without the modulator. The transformers are not
shortened. When I measure the output signal, I obtain a sine around 6
MHz exhibiting a lot of harmonic distortion, on both outputs IoutA2 and
IoutB2. I attached the register files and screen shots of the signal I
measured and screenshots of the settings I used for the multitone software
and for the DAC6582Z software. It would be great, if someone had an idea
what is going wrong with my settings.

Also, is it possible to get the latest version of the multitone pattern
generator software?

Best regards,

Michael Soudan

 

 

4118.tireq.zip

  • 0
    TI__Expert 5820 points

    Michael

    Your configuration settings for using DAC5682z in single DAC mode are incorrect. I have attached the correct settings and I am also listing them below'

    1. The CONFIG10 value is incorrect per page 10 of DAC5682z datasheet. For running the DAC at 1 G, single channel, 2x interpolation, the data rate from FPGA of 3100 into DAC EVM is 1G * (number of DACs)/interpolation = 1G * 1/2 = 1G/2 = 500 M. Since DAC5682z accepts DDR fashion data, the data clock into the DAC is 250 M. Hence CONFIG10 = 0xC8 as specified in the datasheet.
    2. The CDC settings are also incorrect. The clock from CDC to FPGA = DACCLK * (number of DACs)/interpolation/8 = DACCLK * 1/2/8 = DACCLK/16

    I understand that you have removed resistors R137, R153, R155, R156 to disable the modulated output (but then you say put R155 and R156?) I believe when you correct the above mentioned settings, you will get the desired output.

    Regards

    Example_2_mod.zip