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ADS131M08: FIRST Time read Error

Milav Soni
Intellectual 455 points
Part Number: ADS131M08


Hello Team,

This is Milav Soni From Teq Diligent.

I have custom board which have ads131m08 chip available.

I want to read ADC single ended Differential analog input which range is 200uV to 100mV.

I have used "ads131m0x_c_source_code" that is available on ti site for my reference.

before adc data read i call adc_startup api { write 0x510 value to mode register,and all other needed cofiguration}

But When I read mode register after adc data read it is read always "0x511" Value, instead of "0x510"

so i don't know if am i reading correct adc data or not?

I have seen "8.5.1.9.1" section in ads131m08 datasheet, but i don't know how to implement this scenario in code.

can you please help me for the same?

thank you

  • 0
    TI__Guru**** 181441 points

    Hi Milav,

    The details of section 8.5.1.9.1 in the ADS131M08 datasheet are referring to the physical properties of the DRDY pin, not the programming of the MODE register.  The default state of BIT 0 in the MODE register seems like it is set to '1' based on line 76 in the ads131m0x.h file.  Have you commented that line out on your end?

  • 0 in reply to Tom Hendrick
    Intellectual 455 points

    Hello Tom,

    Thank You For Your response.

    No, I have not comment that "DRDY_FMT_PULSE" Macro in my header file.

    But I have question regrading adc data read for first time and after pause, for this any precaution should be taken in firmware?

    I have seen "Code Example" (section 9.1.6) in datasheet, clear the ADC's 2-deep FIFO on the first read.

    is this necessary to do this? means sending dummy word two times for reading actual data?

    In current firmware I have not implemented above 2-deep FIFO features, i got max 6 mV error between Hardware and Firmware voltage reading.

    Is this error coming from due to not present of the above feature? 

    please give me your opinion for the same.

  • 0 in reply to Milav Soni
    TI__Guru 55342 points

    Hi Milav,

    Yes this is necessary to ensure predictable DRDY behavior. If the input to the ADC is changing during this time, then you may see greater than 6mV of error, or read a sample from a previous time. Please see section 8.5.1.9.1 for additional detail. 

  • 0 in reply to Alexander Smith
    Intellectual 455 points

    Hello @ alexander smith

    Thank You For your Response.

    Can you please provide me information how I can reduce this error to near  to 0mv? or how i can resyc mu adc?

    I have tried to give negative pulse in sync/reset pulse of about 245us and waiting for "F_RESYNC" bit to 1.

    But my adc is not getting resync with above functionality.

    ADC CLKIN = 8.192MHZ oscillator.

    SPI Frequency = 4.0MBits/sec

    can you please provide me solution for the same?

    thank you

  • 0 in reply to Milav Soni
    TI__Guru 55342 points

    Hi Milav, 

    You can perform an offset calibration. Connect both inputs to AGND by modifying the MUXn[1:0]  register and record the output value. Invert this value and load into OCALn[23:0]. Section 8.3.11 Calibration Registers for reference.