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ADS1274: ADS1274 drdy timing

Benjamin Nordman
Intellectual 410 points
Part Number: ADS1298
Other Parts Discussed in Thread: ADS1274,

Hello TI Community,

I have a simple question about the table 10 of the ADS1274/8 datasheet.

Does it mean that the /DRDY settle time is 129 * (1 / Fdata)?

e.g. for Fdata = 1kHz => tNDR-SPI = 129ms

Thanks for your help.

Best Regards

Benjamin Nordman

  • +1
    TI__Guru**** 181871 points

    Hi Benjamin,

    Table 10 is related to Figure 72 in the ADS1274 datasheet on page 27.  The /DRDY settle time described here is only applicable when you are changing modes (see table 9 on the previous page).  So, that being said, yes- if you are running at 1kSPS in SPI mode, it would take 129 conversions or 129ms to see the 'new mode valid data ready' output.

  • 0 in reply to Tom Hendrick
    Intellectual 410 points

    Hello Tom,

    Sorry for the name of the topic "ADS1298"... Not really serious! Can you correct it?

    In any case, thanks a lot for your reply.

    Just to be sure, in other cases appart from this one and when the synchronization signal /SYNC is applied (fig.73 p28), the data rate wille always be Fdata?

  • +1 in reply to Benjamin Nordman
    TI__Mastermind 48040 points

    Hi Benjamin,

    I updated the post title to ADS1274.

    This is a similar behavior as the Mode change.  If you are running at 1ksps and you assert the /SYNC pin, this will reset the digital filter and it would take 129 conversions or 129mS to see the next /DRDY and retrieve the next conversion result.  After that initial delay, with /SYNC held high, you will then get data at the 1ksps rate, or every 1mS.

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • 0 in reply to Keith Nicholas
    Intellectual 410 points

    Hello Keith,

    Thanks for the update of the title and for your reply too :-)

    I perfectly well understood how it works then.

    Best Regards,

    Benjamin