Hi
I use Xilinx FPGA and the DAC38J84 to establish the JESD204B developing environment . Now I have some trouble about the SYNC signal. My SYNC can not be toggle. It always stays low. I know CGS is not passed.
The FPGA always transmit the /K28.5/ and I can see the waveform on the oscilloscope . I don't know what's the matter. Does this error come from he registers configuration or the PCB designe? How do I deal with it?
Jim
I have turn to you. I have some questions about the dac38j84 as follows.
1. I map the JESD lane to serdes lane as the imagine. And I config the DATA path A to the DACA, DATA path B to the DACB, DATA path C to the DACC, DATA path D to the DACD. If I transmit the data to the RX1 and RX2 whether I can get the waveform from DACA corresponding to RX1 and RX2.
2. What 's the function of the config 4,config 5, config6. Is there any influence to the usage of the DAC if I mask some alarm and error?
3. What's the function of the serdes fifo. If the fifo is full or empty. How can I modify this error?
Regards
LvZhipeng
Jim
1. I'm sorry. Maybe my description confused you. When I use 8 lanes I map the Serdes lanes to JESD lanes as the first image shows.Whether the output of the DACA is corresponding to the data input to the RX0 and RX1. RX2,RX3 == DACB, RX4 and RX5 == DACC, RX6 and RX7 == DACD.
If I only use two lanes I make the DACB~DACD at sleep mode. I map lane2~lane7 to link1 and map lane0, lane1 to link0. I set sysref_mode_link1 = 000, and sysref_mode_link0 = 001 (config 92 0x0001), I set register config 74' bit15 ~bit8 as 0x03 to only enable the serdes lane0 and lane1. And I map the JESD lanes to the Serdes lanes as the second imagine. If I transmit the data in to RX0 and RX1 whether I can get the output from DACA?
2. If I mask the error and the flag in config4, config5, config6 whether I can ger the alarm and error indication in config 100~108, and the alarm pin.
3. I have made a new board and I replace DAC38J84 with DAC39J84. When I only power the DAC39J84 the output pin IOUTAP~IOUTDP, IOUTAN~IOUTDN have 1.778V output. But the terminal voltage of IOUTAP~IOUTDP, IOUTAN~IOUTDN are -0.5~1.0V described on page6 of datasheet. Why does the default output of the DAC output is so high? Is it right? What's the correct default output voltage of the DAC39J84.
4. My DAC sample rate == 600MHz,
LMF = 841, HD =1 ,k =32, Interpolation rate = 1 , sysref = 9.375MHz, use all sysref mode, I didn't enable DDLY and ADLY in LMK04828.
FPGA Virtex7 xc7vx690T.
FPGA reference clk = 150MHz, serdes rate = 6Gbps. Serdes PLL output is 3GHz, Half rate. I can see the waveform on the oscilloscope through alarm pin, the frequency is serdes pll output/80 == 37.5MHz.
The config108 shows the serdes PLL is locked.
My operation sequence :
(1) Power the FPGA, DAC39J84 and LMK04828. SYNC_N_AB and SYNC_N_CD are logic high.
(2) Reset the Xilinx JESD204B IP core and make the JESD204B IP core still reset,The transmitter doesn't transmit any character.
(3) Config DAC39J84, the SYNC _N_AB and SYNC_N_CD are still high.
(4) Config LMK04828, DACCLK and sysref are provided to the DAC39J84. SYNC _N_AB and SYNC_N_CD are pulled to low. That is to say DAC39J84 transmit a sync request.
(5) Remove the reset signal to make the JESD204B IP core normal operation, SYNC_N_AB and SYNC_N_CD are pulled to high and still high.
I only use two lanes in this operation. I only enable serdes lane0 and serdes lane1 and make DACB~DACD at sleep mode. SYNC_N_AB and SYNC_N_CD are mapped to link0. The data was input to the RX0 and RX1. The serdes lanes are mapped to the JESD lands as the imagine. I set sysref_mode_link1 = 000, and sysref_mode_link0 = 001 (config 92 0x0001).
I config the registers config81 and config82 as 0xFF,0xFF. The SYNC_N_AB and SYNC_N_CD are still high. I read config 65 , the errcnt_link0 ==0 . That is to say there are no errors described in the config81 and config82. Right? Is it mean that the GCS and ILA has passed?
But I read config 100 and config101 registes as 0x0703,0x0703. And the DACA doesn't have output. How do I do? Which error indicators registers should I believe? config100,101 or config 81,82, 65.
Jim
When I use eight lanes, SYNC will be assert about 360ns and then be pull down. The SYNC takes on a period waveform just like the first imagine.
I transmit a square wave from FPGA and I get a waveform just like the second imagine. It is not what I want. But it seems like there some output on the DAC'S.
I take off the error on the registers config 81. I set the config 81 as 0x0080,0x0040,0x0020,0x0010,0x0008,0x0004,0x0002,0x0001 respectively. When I set the config 81 as 0x0020 the SYNC will be a period waveform. As for the other configurations SYNC is high all the time. Maybe I think the trouble is on the configuration between the FPGA and DAC38J84 about the JESD204b parameter. But I inspect the configuration about LMF K
S,CS, CF,HD,N,N' and so on. The parameter between the FPGA JESD204B IP core are the same. I read the config 100 to 107 as 0x270b.
I don't know which error indicator should be reliable. Is it really the trouble from parameters configuration? In addition, why are the serdes fifo full or empty. And as your reply it is the problem about the clock frequency,
but I don't think my clk frequency is wrong.
DAC sample rate = 600MHz, lane rate = 6Gbps.
Serdes PLL reference clk = 600MHz, MPY = 5, Serdes rate = half rate. I can get 37.5MHz signal at the alarm pin.
FPGA reference clk = core clk =150MHz
Regards
Zhipeng
Jim
I can see the K28.5 comma data on the oscilloscope as the following picture.
1.In the previous post, I didn't start the DAC as the sequency you said. After reading your reply I tried the setup order as what you said. Until I operate to the step 15 I read config 100 to 107 as 0x0001. Then I clear the config100 to 107 as 0x0000. After that I read config 100 to 107 again . They are all 0x0000. config 108 == 0x0003, config 109 == 0x0000. The SYNC is always asserted. Whether it means that there are no errors.
2.I found an interesting things. I write the other number to config 100 to 107 and then I read back. I found what I read back are what I wrote to config100 to 107. If I set a link configuration error on purpose when I program the DAC39J84. I read the config100 to 107. They are all 0x2001. Then I clear them and read back. I found they are also 0x2001. Does it mean that if there are no errors config100 to 107 can be write as what user's want. If there are errors the error bits are asserted and the clear operation can not clear them until the correct status present.
3. When the TX transfer K28.5 I found the SYNC can also be asserted without SYSREF. Is it normal?
Jim
I read the file that you provide to me. I saw the trace length of Device clock and the SYSREF are matched as the following picture shows. Whether the trace length of Device clock and SYSREF to the same device must be same? If the length of Device clock and SYSREF are different whether the DAC39j84' work status will be influenced. The difference of the trace length between Device and SYSREF on my board is within 40mils.
Regards
Zhipeng
