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ADC12DJ3200: SPI programming sequence
Part Number: ADC12DJ3200
My Configuration Files as:
ADC12DJxx000x0000 0xB0 // Do soft reset0x0200 0x00 // Clear JESD_EN (always before CAL_EN)0x0061 0x00 // Clear CAL_EN (always after JESD_EN)0x0201 0x00 // Set JMODE00x0202 0x03 // Set KM1=3 so K=40x0204 0x01 // Use SYNCSE input, offset binary data, scrambler enabled0x0213 0x07 // Enable overrange, set overrange holdoff to max period 8*2^7 = 1024 samples0x0048 0x03 // Set serializer pre-emphasis to 30x0061 0x01 // Set CAL_EN (always before JESD_EN)0x0200 0x01 // Set JESD_EN (always after CAL_EN)0x006C 0x00 // Set CAL_SOFT_TRIG low to reset calibration state machine0x006C 0x01 // Set CAL_SOFT_TRIG high to enable calibration
ADC DCLK: 3200MHz;
when input a sine wave(3.2MHz), output wave as:
rx_data0:s0,rx_data1:s1, ... ,rx_data19:s19;
can you help me to analyze a problem mentioned above? any error in configratiom file?
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In reply to Jim Brinkhurst84999:
iladata_3.2MHz.7zThe attachment have the data you wanted.Plesse tell me,What would I like to do about it?Thanks!
In reply to user5615265:
I"m sorry.There is someting wrong with the data that has been given to you!data_3.7z
This data file has two data,for register 6C=00 and register 6C=01,file named as "iladata_6C00" or "iladata_6C01" .THANKS
I have reviewed the file with register 6C = 01. The raw data for each GTx receiver appears to be correct. I added some columns to the file and added information showing the parsed out sample and tail bit values at the top of the file and again at the bottom (around row 1000) to verify the data stays correct through the record.
Since the raw data looks correct I think there must be some issue with the JESD204B IP configuration.
If you haven't already done so, please check out this Xilinx KCU105 JESD204B reference design firmware targeting the ADC12DJ3200. That may help you find where the problem with your current implementation is located.
I hope this is helpful.
Many thanks!The problem has been solved.
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