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Sync rules for SPI command in DAC80004

Intellectual 350 points

Replies: 17

Views: 137

Hello, Regarding the SYNC (CHip Select)  laws of Dac80004.
1.What is the Maximal amount bits I can send over MOSI for a single Low Sync(Chip select) session?
2.What is the minimal amount of time SYNC (Chip select) has to be high in order for the DAC to recognise that the SPI sesion is OVER?
3.If i Send my 32 bit command in 4 different 8bit Sync sessions,will the Dac recognise it as a valid command of 32bits?

Thanks. 

www.ti.com/.../dac80004.pdf

  • Hi,

    Please find my answers inline.

    1.What is the Maximal amount bits I can send over MOSI for a single Low Sync(Chip select) session?

    I mean you wanted to ask how many commands you can send by keeping SYNC low, right? its one SPI command per frame. That means 32 bits

    2.What is the minimal amount of time SYNC (Chip select) has to be high in order for the DAC to recognize that the SPI session is OVER?

    35nS

    3.If I Send my 32 bit command in 4 different 8bit Sync sessions, will the DAC recognize it as a valid command of 32bits?

    No, SYNC has to stay low for one complete SPI frame ( that is for 32 bits)

    Regards,

    AK

  • In reply to Akhilesh K:

    Hi,

    Any update on this issue? Do you need more help?

    Regards,

    AK

  • In reply to Akhilesh K:

    Hello :-) thank you for remmembering.
    I am currently working on another device and i hope i get a good SPI signal to shown you as soon a possible regarding the DAC80004.
    Thanks again for remmembering.

  • In reply to yefj smith:

    Hi,

    Will wait for your scope shots and updates.

    Regards,

    AK

  • In reply to Akhilesh K:

    LDAC=0 CLR=1

    //W/R=0 write and update channeL0 all1 data dont cate
    // {00000011,b00001111,11111111,11110000}; channel 0(register 0) write FFFF expect to get full scale VDD
    first command {0x03,0x0F,0xFF,0xF0}

    Second command: enable DSO second bit is one to enable {0x08,0x00,0xFF,0x02}

    third command:NOP command {0x0E,0x00,0x00,0x00}

    I am sending my command in 8bits peaces so as you can see that is a gap in clock signal between subtransmitions,but as i understood its not a problem as long as SYNC is low.

    I have attached the SDIN vs CLK in every command in a description in them with step by step enumiration
    I dont get any output at SDO i am supposed to get the data i put at the channel0 register which is all 1,but i get 0 response.

    Where did i go wrong?

  • In reply to yefj smith:

    Hi,

    These data frames looks fine to me. Whats the SPI clock frequency here?

    Also can you try without any gap between the SPI Clocks if possible?

    Please don't repost the same in the other thread, we will continue this discussion here, I will close the other thread, it creates unnecessary confusion for me.

    Regards,

    AK

  • In reply to Akhilesh K:

    the clock is 1Mhz. is it ok?

  • In reply to yefj smith:

    Hi,

    One more question, are you facing issues with read only or you are not able to get the DAC outputs working?

    Please share SDO frame as well for better understanding of the read frame. I want last two frames together in scope shot, meaning for reading you will send two frames, one will be read frame and second will be NOP frame

    Regards,

    AK

  • In reply to Akhilesh K:

    Hello Akhilesh,I will send the printscreens of scope as soon as possible.
    I have a fundamental question:
    is it ok with the device to send a comand in 8 bit peaces when CS is low the whole time and there is a small clock stop between 8bit packet transfer as shown bellow?
    Thanks.

  • In reply to yefj smith:

    Hi,

    No issues, you can send command like 4 packets of 8 bits with SYNC held low.

    Regards,

    AK

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