DAC38J82EVM: JESD204b byte frame

deepak kumar32

Part Number: DAC38J82EVM

For 8 lane config and LMF =821 as in datasheet, each lane has 24 bits to be accommodated in frame (Table 9 of datasheet). When we pack data in FPGA, should we keep the remaining bits as zeros as shown below in figure. We have to pack 256 bits for the frame in FPGA for 8 lane config.

Thanks,

over 8 years ago

0 jim s over 8 years ago

TI__Guru* 91947 points

0804.TSW14J56 RevD MC firmware design document.doc 1856.JESD204_TI_reference_design.pdfDeepak,

Your think of this is wrong. Please take a look at the attached documents for more info regarding how the parallel data is formatted after it leaves the JESD block.

Regards,

Jim

0 deepak kumar32 over 8 years ago in reply to jim s

Intellectual 350 points

Hello Jim,

You have given me the docs for Altera FPGA. I am using Xilinx FPGA.

Following shows what I translated from Xilinx JESD doc for a LMK=821. The last 64 bits do not have any data, based on DAC datasheet. I am not sure but it is not very clear, whether NO DATA section need to be filled with subsequent data.

Please clarify.

Thanks,

0 jim s over 8 years ago in reply to deepak kumar32

TI__Guru* 91947 points

Deepak,

The data sheet used blank columns to separate the different mode options. There is no blank data. One of the two documents I sent was actually a Xilinx example of how the data is formatted in the firmware.

Regards,

Jim

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DAC38J82EVM: JESD204b byte frame