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ADS54J54EVM: Read DDR to file TIMED_OUT_ERROR (TSW14J56 Rev E)

Andrew Greensted
Prodigy 250 points

Part Number: ADS54J54EVM
Other Parts Discussed in Thread: ADS54J54, LMK04828

I have the following two evaluation boards.

  • ADC Board: ADS54J54EVM Rev C
  • FPGA Board: TSW14J56 Rev E

I'm following the instructions from Section 3.3.3 and 3.3.4 from SLAU616A. However, when I attempt a capture, I receive a Read DDR to file TIMED_OUT_ERROR message.

Here is the sequence of steps I followed:

Connect ADC Board to FPGA Board
Connect 5V supply to ADC Board and power on (Using provide PSU)
Connect 5V supply to FPGA Board and power on (SW6 to ON) (PSU rated to 20A)
Connect ADC Board USB cable to PC
Connect FPGA Board USB cable to PC
Connect a 10MHz sinusoid (50mVpp) to J22 (Chan D +)
Start ADS54J54 EVM GUI (Build Date 12/18/14, Prelim devbug)

Check for Green LED Icon on USB Status

On ADS54J54 -> ADC Configuration Tab check 'Device Reset' checkbox
On LMK04828 -> PLL1 Configuration Tab check 'RESET' checkbox
On Low Level View Tab, click 'Load Config' button
Select ADS54J54_500M_442.cfg
The following 6 screen shots show the GUI state after the config file has been loaded
Checked ADC Board LEDS:
- D1 LMK Locked is illuminated
- D4 PLL2 Locked is illuminated
- D3 JESD_SYNC is illuminated, but it is very faint
Disabled Group Powerdown for CLKOut 6 and 7
Set CLKOut 7 to LVDS
Confirmed 250 MHZ on SMA J10 (CLKOut 6) - This should be the same as JESD Core Clock going to FPGA
Confirmed 1.5625 MHZ on SMA J17 (CLKOut 7) - This should be the same as JESD Core SYSREF going to FPGA
The screen shot below shows the change in settings to allow 'copies' of the JESD Clock and SYSREF to be observed.

Start High Speed Data Converter Pro v4.90

  • Dll version 0.1
  • Firmware version 0.2
  • No Patch Applied
The software hangs for 150 seconds. The grey and black progress bars just scroll.
I suspect some kind of network access that is slowly timing out.
The Select Board Dialog appears. Select the board from the list and click OK
The following dialog appears:
'No firmware. Please select a device to load firmware into the board'
Click OK
Click the green arrow next to Select ADC
Select 'ADS54J54_LMF_442' from list
The following dialog appears:
'Do you want to update the Firmware for the ADC?'
Click Yes
These are the states of the FPGA board LEDs
D28 CONFIG_DONE is illuminated
D8 MEM FAIL~ is illuminated
D7 MEM SUCCESS~ is off
D6 MEM INIT DONEE~ is off
D4 RX CLK is off
D3 RX SYNS~ is illuminated
D2 TX CLK is off
D1 TX SYNS~ is illuminated
ADC Board LED D3 (JESD_SYNC) is still faintly illuminated
Enter 250M in the ADC Output Data Rate Box
The following dialog appears:
'New lane rate is 5G due to ADC Output Data Rate change'
'JESD reference clock from device EVM to TSW14J56revD needs to be set at 250M
Click OK
Click Capture
Get Read DDR to file TIMED_OUT_ERROR message as shown in the screen shot below.
Here's some things I've tried/observed.
  • All the blue LEDS on the FPGA board are illuminated
  • The error message states D4 LED should be blinking. I'm assuming this is D4 on the FPGA board (RX CLK); I've only seen this on or off, not blinking
  • The HSDC Pro software mentions RevD of TSW14J56, I have Rev E.
  • I've tried other USB ports, but this hasn't helped
  • The LMK04828 is configured for LVPECL on the ADS54J54 SYSREF input. The ADS54J54 datasheet states these are LVDS inputs

Hope someone can help.
Thanks
Andy

  • 0
    TI__Guru* 91947 points

    Andrew,

    We are looking into this issue.

    Regards,

    Jim

  • 0 in reply to jim s
    TI__Guru* 91947 points

    Andrew,

    The ini file used by HSDC Pro GUI is selecting the wrong firmware file. After you have opened HSDC Pro GUI and selected the device, do not let the GUI download the firmware. Instead click on "Instrument Options" in the top left of the GUI, then select "Download Firmware". A new window will open. Select the file called "TSW14J56REVD_RX_ALT_SYNC_LVDS_FIRMWARE.rbf". This will provide the dual LVDS JESD SYNC signals required by the ADC with the default settings used with the config file you loaded.

    Regards,

    Jim 

  • 0 in reply to jim s
    Prodigy 250 points

    Hi Jim,

    Many thanks for your help. I can now successfully capture data from the board. Please could you take a look at my other queries at the bottom of this post.

    For those who might have a similar issue, here are the steps I followed (following on from my first post):

    ADS54J54 EVM SPI GUI
    For a 10MHz input on Chan D
    On ADS54J54 -> ADC Configuration Tab Set Decimation Filter CD to 'Low Pass'

    Start High Speed Data Converter Pro v4.90
    The Select Board Dialog appears. Select the board from the list and click OK
    The following dialog appears:
    'No firmware. Please select a device to load firmware into the board'
    Click OK
    Select 'Instrument Options -> Download Firmware'
    Select File 'TSW14J56REVD_RX_ALT_SYNC_LVDS_FIRMWARE.rbf'
    Click OK
    Click the green arrow next to Select ADC
    Select 'ADS54J54_LMF_442' from list
    The following dialog appears:
    'Do you want to update the Firmware for the ADC?'
    Click No
    These are the states of the FPGA board LEDs
    D28 CONFIG_DONE is illuminated
    D8 MEM FAIL~ is illuminated
    D7 MEM SUCCESS~ is off
    D6 MEM INIT DONEE~ is off
    D4 RX CLK is off
    D3 RX SYNS~ is illuminated
    D2 TX CLK is off
    D1 TX SYNS~ is illuminated
    ADC Board LED D3 (JESD_SYNC) is still faintly illuminated
    Enter 250M in the ADC Output Data Rate Box
    The following dialog appears:
    'New lane rate is 5G due to ADC Output Data Rate change'
    'JESD reference clock from device EVM to TSW14J56revD needs to be set at 250M

    Click OK
    Click Capture
    These are the states of the FPGA board LEDs
    D28 CONFIG_DONE is illuminated
    D8 MEM FAIL~ is illuminated
    D7 MEM SUCCESS~ is off
    D6 MEM INIT DONEE~ is off
    D4 RX CLK is flashing
    D3 RX SYNS~ is off
    D2 TX CLK is off
    D1 TX SYNS~ is illuminated
    ADC Board LED D3 (JESD_SYNC) is still faintly illuminated
    Other Queries
    • Why does HSDC Pro not respond for 150 seconds at start-up. This is quite annoying.
    • I mentioned in my first about a discrepancy in the differential standard for the ADS54J54 SYSREF input, should this be LVDS rather than LVPECL
    • Does D3 (JESD_SYNC) on the ADC board actually do anything? It seems to always be faintly lit.
    HSDC Pro Crashes
    I've had HSDC Pro crash at least 4 times now. Here is one of the error dialogs:
  • 0 in reply to Andrew Greensted
    TI__Guru* 91947 points

    Andrew,

    See the attached document for help with your HSDC pro issue. Regarding D3, in the past, the firmware team has used this diode as a SYNC indicator but I have seen newer versions of firmware not drive this LED. I have a feeling this connection to the FPGA is floating.

    Regards,

    Jim

    HSDC Pro GUI Labview issue.docx

  • 0 in reply to jim s
    Prodigy 250 points

    Thanks again for your help Jim. HSDC Pro seems to be more stable with the updated LabView Runtime Engine.

    However, I'm still experiencing the very long unresponsiveness at start-up. Perhaps this could be fed back to the design team. As I mentioned before, this has the feel of a network time-out issue. If this is the case, I don't see why the software would be attempting a network connection; perhaps checking for updates?

    Thanks

    Andy

  • 0 in reply to Andrew Greensted
    TI__Guru* 91947 points

    Andrew,

    Here are some suggestions to try from our software team:

    1. Do we know if the user tried different HSDC Pro version on that machine? Or is it only happening with a specific HSDC Pro version?

    2. Can we ask the customer to restart the machine if not tried already.

    3. Is the issue only with loading HSDC Pro and not with ADS54J54EVM GUI?

    Regards,

    Jim

  • 0 in reply to jim s
    TI__Guru* 91947 points

    Andrew,

    More from software team:

    It seems that the GUI tries connecting to the network every time it is launched to check for any updates (details given below).

     

    HSDC Pro checks for updates every 7 days and stores the last checked date in an INI file (“Settings.ini” in HSDC Pro Data folder). If the update was not successful (due to some network issues) this file will not be updated with the current date which means the update is not performed. So every time the GUI launches, HSDC Pro sees the last checked date is more than 7 days and tries  connecting to the network.

     

    Kindly suggest the customer to,

    1.       Connect to the internet

    2.       If connecting to the internet is not possible, update the “Settings.ini” file at “C:\Users\Public\Documents\Texas Instruments\High Speed Data Converter Pro” manually by following the steps given below,

    a.       Open “Settings.ini” file

    b.      Find “Last Checked” key at the bottom of the file

    c.       Update the date in the following format – “MM/DD/YY”

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 250 points

    Hi Jim,

    That's sorted it! Many thanks to you and TI for investigating this. I've set the value to a date in the future to hopefully avoid further attempts to look for an update.

    Andy