ADS5294: 2-wire, Decimation by 2

Zain Riaz

Part Number: ADS5294

Dear Team,

A customer wants to use ADS5294 as a 2-wire setup, with the decimation by 2 filter enabled @ 62.5MHz. The datasheet does not seem to provide much information on such a setup.

To be certain, I will appreciate if we can provide setup and hold times for a situation like this to the customer.

Additionally, for the bitclock frequency calculation, they asked if the following calculation should be valid:

(62.5MSPS*14bit)/2 wires/2 decimation/2 DDR = 109.375MHz.

I look forward to the support.

Thanks and Regards,
Zain Riaz

over 6 years ago

0 Xiaochen (Sean)Xu over 6 years ago

TI__Expert 6040 points

the cacluation is correct. while based on most FPGA speed, 1-wire mode can support this very easily. that is why we don't expect cusotmer using 2-wire mode.

please refer to datasheet regtister maps for setting up 2-wire , register 0x46

EN_2WIRE 1: 2-wire LVDS output; 0: 1-wire LVDS output. Note: ~250us PLL settling time is required after programming the EN_2WIRE bit from Default States After Reset

for the timing, datasheet section 8.8 gave out the timing . their Fs is equlvient as 32.5Mhz, so they can use 30Mhz timing data.

Thanks!

0 Johan C over 6 years ago in reply to Xiaochen (Sean)Xu

Prodigy 20 points

Hello Xu,

Thanks for the reply, we understand that this is an unusual situation. But we would like to use it due to limitations in the system.

Our question was initiated by the included note from the datasheet. This would mean we need to apply a correction to the timing given in table 8.8.
Is this correction always -70ps for the set-up time and -0ps for the hold time?

Thanks in advance

Kind Regards

Johan

0 Xiaochen (Sean)Xu over 6 years ago in reply to Johan C

TI__Expert 6040 points

Johan

yes. you can add the 70ps margin in the timing. because the LVDS data rate is low, you should have enough margin on the FPGA side.

Thanks!

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ADS5294: 2-wire, Decimation by 2