Hi,
My customer has a related question.
Their configuration is as follows.
[Q]
Why is this setting invalid PLL frequency ?
My understanding as follows.
- High VCO accept this DAC frequency.
- Internal PLL for DACCLK can generate in this configuration.
- SerDes PLL can generate the serdes clock.
Therefore why ... ?
Best Regards,
Hiroshi Katsunaga
