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ADS1298: Non-standard sampling frequency.

Currently setup to run in continuous mode at 250 samples per second. Processor interrupted with DRDY and goes and gets the samples. Works fine. DR="110" according to table 2 of spec. Low power mode.

Our client wants to use an external (more accurate) timing reference which is to result in 256 samples per second (one sample every ~3.91ms). The plan was to have it use the "one-shot" mode instead and then just control when data is read by the external CPU by wiggling the START pin. Would prefer to leave it running off of internal 2.048MHz clock and just control when samples are collected.

But table 12 in the spec says that in low power mode with DR="110", it takes 36872 clock for data to settle. That's 18ms. (An experiment confirmed this.) With DR="011" it *is* fast enough, but would (presumably) be more noisy and less sensitive.

In continuous mode, with DR="110" data is ready every 4ms. It appears that if you set DR="101" at 500 SPS but only read out of the device at 256 SPS, then samples are being dropped, so that is bad. It does not appear there is a continuous mode where not reading a sample will stall the "pipeline", so an external clock can control it that way.

Questions:

1) Is my understanding correct?

2) Is there a way to do 256 samples per second?

Thanks...

  • Hey Klaus,

    1) Yes I believe your understanding is correct. The unfortunate reality of delta sigma converters is that you must abide by a single modulator clock which tends to dictate so much of the system timing.

    2) Yes, there are a couple of ways. If you definitely still want to use the internal clock, you could do like you mentioned and use a faster data rate in single shot mode so the data settles fast enough for you to collect at 256 SPS. You are correct in your assessment that you would face degraded noise performance since the bandwidth is higher using a higher data rate. The second way would be to use an external 2.097152 MHz clock and then the "250 SPS" data rate will occur at 256 Hz.

    Regards,
    Brian Pisani