Because of the holidays, TI E2E™ design support forum responses will be delayed from Dec. 25 through Jan. 2. Thank you for your patience.

  • State Resolved
  • Locked Locked
  • Replies 11 replies
  • Answers 4 answers
  • Subscribers 28 subscribers
  • Views 771 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DLP3021LEQ1EVM: FPGA program for DLP3021LEQ1EVM and DMD monochrome mode (static mode)

Vladimir Zhukov
Intellectual 370 points
Part Number: DLP3021LEQ1EVM
Other Parts Discussed in Thread: DLP3021-Q1, MSP430G2553-Q1

Hello!

Tell me, please:
1. Can DLP3021LEQ1EVM be used as a monochrome micromirror control system (without RGB LEDs)?

2. Is it possible to set a constant static mode of micromirrors with monochrome irradiation (not RGB)?

To display one or more pixels (on / off).

3. Can you change the FPGA code for your development?

4. Is it possible to replace the DLP3021 matrix with a Martrix in the IR (NIR) range for the same FPGA controller?

Best regards, Vladimir Zhukov.

  • 0
    TI__Mastermind 27940 points

    Hello Vladimir,

    1. Yes, the DLP3021-Q1 can support a monochrome or white-only LED. DLP Composer uses the red channel for single LED output mode. To generate a single channel output with DLP Composer, you need to change the sequence duty cycles to R=100, G=0, B=0 in, and then change your image format to “grayscale” on the image/video tab in Composer:

    You’ll see that the sequence is repeated twice per frame. The frame rate is still 25Hz but the subframe rate is higher (50Hz). This is true for the RGB and single color sequence.

    2. DLP3021-Q1 supports either dynamic or static content regardless of the LED type. 

    3. Certain elements of the FPGA code/firmware are user configurable by the DLP Composer project/UI.

    4. We have not explored pairing NIR with our DLP module. Only LED and laser light sources are currently supported. Could you elaborate on your intended NIR use-case?

  • 0 in reply to Akeem Whitehead
    Intellectual 370 points

    Hello Akeem,

    I still have clarifying questions:

    3. In what programming language is the program for FPGA written so that I can change it myself?

    4. In our task, it is necessary to work both in the visible range of 400-780nm, and in another version in the IR range of 800-1400nm.

    The task is to create a spatial (shading / reflective) filter in the path of laser radiation that is directed to the matrix. The position of the pixels in the matrix must be kept constantly in one position. It is highly desirable to disable frame sequencing (we are using only one image) and disable global reset of mirrors.

    Best regards, Vladimir Zhukov.

  • 0 in reply to Vladimir Zhukov
    TI__Mastermind 27940 points

    Vladimir,

    3. The FPGA source code is not directly accessible to customers. DLP Composer is the only tool that allows you to partially modify aspects of the FPGA firmware prior to it being built/compiled in the background of the tool.

    4. Sequencing on the DLP3021-Q1 will always require a global reset since our maximum supported mirror on/off duty cycle is 99/1 (100/0 currently not available). The DLP3021-Q1 was not intended to be used in the type application you have described, but as long as your visible and IR light sources are compatible with the driver hardware, and the resolution requirement of both is WVGA, the DGP electronics may be an option. Have you also considered the DLP-Pico catalog? Their solutions may offer more flexibility in regards to your firmware and sequencing requirements.

  • 0 in reply to Akeem Whitehead
    Intellectual 370 points

    Akeem good day!

    3. What part of the program can be reprogrammed in FPGA through DLP Composer?
    What exactly is available to change the FPGA code?

    Best regards, Vladimir Zhukov.

  • 0 in reply to Vladimir Zhukov
    TI__Mastermind 27940 points

    Hi Vladimir,

    If you download DLP Composer for DLP3021-Q1 (Rev. A), and import the DLP3021-Q1 Composer Project and FPGA Configuration 1.2 (Rev. A) project, you can see all the registers and settings that you can configure as part of the FPGA.

  • 0 in reply to Akeem Whitehead
    Intellectual 370 points

    Akeem good day!

    3. What demo code can Texas Instruments provide for the FPGA in Vivado so that I can optimize it for myself? 

    (not the firmware code from DLP Composer)

    Best regards, Vladimir Zhukov.

  • 0 in reply to Vladimir Zhukov
    TI__Mastermind 27940 points

    Hi Vladimir,

    The FPGA code is closed-source as its configuration is always built as a binary output by DLP Composer. The FPGA should be viewed as a fixed function controller specifically designed to for the DLP3021-Q1, so it's not as flexible as a traditional microcontroller/processor.

    We do offer example code (MSP430 Example Code 1.2 (Rev. B)) for an external MSP430G2553-Q1 microcontroller to interface to the FPGA to call register read/writes and its pre-defined functions.

  • 0 in reply to Akeem Whitehead
    Intellectual 370 points

    Akeem good day!

    3.Can I get this code for FPGA by pre-signing an NDA non-disclosure agreement?

    This may have greatly simplified my task.

    Best regards, Vladimir Zhukov.

  • 0 in reply to Vladimir Zhukov
    TI__Mastermind 27940 points

    Hi Vladimir,

    Unfortunately, we currently have no plans to make the FPGA source code available to external users. I can send you an update if our plans change.

  • 0 in reply to Akeem Whitehead
    Intellectual 370 points

    Akeem good day!

    3. Tell me, does DLP Composer generate a new version of the FPGA firmware with my parameters set ?

    Or does DLP Composer only send configuration parameters to the FPGA?

    Best regards, Vladimir Zhukov.

  • +1 in reply to Vladimir Zhukov
    TI__Mastermind 27940 points

    DLP Composer generates a new version of the FPGA firmware with the parameters set. The DLP3021LEQ1EVM Evaluation Module user's guide section 4.1.6 Flash Blocks provides a breakdown of the flash memory partitioning, and where the FPGA configuration is stored as part of the single binary file generates by DLP Composer.