Other Parts Discussed in Thread: DLP4710
Hi,
I want use a FPGA to process a Trigger-Input signal, and want "real-time" show up pattern on DMD (send VSYNC to DLPC3479) in external pattern mode (2D pattern).
A pre-load pattern (1st frame) will be send from FPGA to DLPC3479 in the IDLE state, then waiting for the Trigger-In signal.
Once FPGA receive tigger-in, send VSYNC and 2nd frame at the same time.
My question is, there is a 10~60Hz FPS range in spec, and the time interval between two Trigger-in is sometimes greater than 0.1sec.
DLPC3479 & DLP4710 will keep the 1st frame in internal frame buffer?
Thanks!
Daniel
